Equalizer and transmitter including the same

Patent metadata

Field	Value
Publication number	US-11515859-B2
Application number	US-202117372744-A
Country	US
Kind code	B2
Filing date	Jul 12, 2021
Priority date	Jun 11, 2018
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

First claim

What is claimed is:

1. An equalizer comprising:
a shift register configured to provide a symbol sequence extracted from serial data;
a plurality of first registers configured to receive the symbol sequence and generate an equalized digital signal corresponding to the symbol sequence;
a plurality of second registers configured to store a value provided from outside the equalizer, wherein an output of the plurality of second registers is directly connected to the plurality of first registers;
a filter controller configured to control the plurality of second registers to output a value and further configured to control the plurality of first registers to store a value provided by the plurality of second registers; and
a digital-to-analog converter configured to convert the equalized digital signal into an equalized signal.

2. The equalizer of claim 1 , wherein:
the plurality of second registers store values of the equalized digital signal grouped into a plurality of data sets corresponding to a plurality of filter coefficient sequences, and
the filter controller is further configured to control the plurality of first registers to load one of the plurality of data sets.

3. The equalizer of claim 1 , further comprising:
an offset generator configured to provide an offset of the equalized digital signal corresponding to a variation of a filter coefficient; and
a calculator configured to perform an addition or subtraction on at least two of: (1) the values stored in the plurality of second registers, (2) values included in the plurality of first registers, and (3) the offset, wherein
the filter controller is further configured to receive a control signal from outside the equalizer, provide the variation of the filter coefficient to the offset generator based on the control signal, and control the plurality of first registers to load an output value of the calculator.

4. The equalizer of claim 3 , wherein the offset generator comprises a plurality of third registers configured to output a step size corresponding to a pair of a filter coefficient and a symbol.

5. The equalizer of claim 4 , wherein the offset generator comprises:
a counter configured to generate a count value which is increased, decreased, or maintained according to the variation of the filter coefficient; and
a multiplier configured to output the offset by selectively changing a sign of the step size according to the variation of the filter coefficient.

6. The equalizer of claim 4 , wherein the filter controller is further configured to refresh the plurality of third registers based on the control signal.

7. The equalizer of claim 4 , wherein the offset generator comprises a counter configured to output a count value that increases or decreases according to the variation of the filter coefficient.

8. The equalizer of claim 7 , wherein the filter controller is further configured to repeat refreshing of the plurality of first registers until the count value becomes zero if the variation of the filter coefficient corresponds to a reset of the filter coefficient.

9. The equalizer of claim 3 , wherein the filter controller is further configured to perform clock gating of at least one of the offset generator and the calculator after refreshing the plurality of first registers.

10. The equalizer of claim 1 , wherein the plurality of second registers are rewritable and configured to store values of the equalized digital signal according to an externally received signal.

11. The equalizer of claim 1 , wherein the symbol sequence includes 2-bit symbols.

12. A transmitter for transmitting input data through a channel, the transmitter comprising:
a serializer configured to generate serial data from the input data;
an equalizer comprising:
a finite impulse response (FIR) filter block configured to use a lookup table that outputs a digital signal corresponding to a symbol sequence extracted from the serial data, and
a digital-to-analog converter configured to output an equalized signal by converting the digital signal; and

a driver configured to amplify the equalized signal, wherein:
the FIR filter block is configured to:
refresh the lookup table based on channel information received through the channel, and
adjust previously-applied offsets if a variation of a filter coefficient corresponds to a reset of the filter coefficient.

13. The transmitter of claim 12 , wherein the FIR filter block further comprises a data storage for storing values of the digital signal corresponding to potential symbol sequences and is further configured to refresh the lookup table based on at least one of the values stored in the data storage and values included in the lookup table.

14. The transmitter of claim 13 , wherein:
the data storage stores values of the digital signal grouped into a plurality of data sets corresponding to a plurality of filter coefficient sequences, and
the FIR filter block refreshes the lookup table by loading one of the plurality of data sets.

15. The transmitter of claim 12 , wherein the FIR filter block is configured to:
receive a control signal from outside the equalizer,
generate an offset of the digital signal corresponding to a variation of a filter coefficient, and
refresh the lookup table based on the offset of the digital signal.

16. The transmitter of claim 15 , wherein the FIR filter block is configured to generate the offset of the digital signal based on a step size corresponding to a pair of a filter coefficient and a symbol.

17. The transmitter of claim 12 , wherein the equalizer is configured to perform clock gating of at least a part of the equalizer after refreshing the lookup table.

18. The transmitter of claim 12 , wherein the symbol sequence includes 2-bit symbols.

19. An equalizer comprising:
a shift register configured to extract a sequence of symbols from serial data;
a digital equalizer circuit configured to generate a digital signal, corresponding to the sequence of symbols, that is equalized to compensate for a characteristic of a communication channel; and
a digital to analog converter configured to convert the digital signal into an analog signal, wherein:
the digital equalizer circuit is configured to:
change a value of the digital signal by an amount determined by a first symbol within the sequence of symbols and a coefficient of equalization corresponding to the first symbol,
increase the value of the digital signal by the amount determined by the first symbol in response to determining the characteristic meets a first criterion, and
decrease the value of the digital signal by the amount determined by the first symbol in response to determining the characteristic does not meet the first criterion.

20. The equalizer of claim 19 , wherein:
the sequence of symbols is one of a plurality of mutually-exclusive potential sequences of symbols, and
the digital signal is one of a plurality of mutually-exclusive potential digital signals.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Gun-Il
• Lee June-Hee
• Cho Byung-Wook

Classifications

• H04L25/03006 Primary

  Arrangements for removing intersymbol interference · CPC title

• H03H17/0227

  Measures concerning the coefficients · CPC title

• H04L25/03343

  Arrangements at the transmitter end · CPC title

• H03H17/06 Primary

  Non-recursive filters · CPC title

• H03M3/324 Primary

  characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement · CPC title