High-speed signaling systems with adaptable pre-emphasis and equalization

Patent metadata

Field	Value
Publication number	US-9553745-B2
Application number	US-201213452513-A
Country	US
Kind code	B2
Filing date	Apr 20, 2012
Priority date	Jan 20, 2005
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

First claim

What is claimed is:

1. A first integrated circuit, comprising:
a transmitter having a transmit equalizer operable to equalize first data to be transmitted to a second integrated circuit; and
a receiver having a receive equalizer operable to equalize second data to be received from the second integrated circuit;
where the first integrated circuit is operable to implement at least two different modes, including
a first mode, in which the transmit equalizer and the receive equalizer are each operable to mitigate intersymbol interference arising from respective, different symbol latencies relative to a main bit of the first data and a main bit of the second data, respectively, and
a second mode, in which a specific symbol latency addressed by the receive equalizer in the first mode is not addressed by the receive equalizer relative to the main bit of the second data, and in which the transmit equalizer is configured to address intersymbol interference arising from a symbol of latency relative to the main bit of the first data which matches the specific symbol latency.

2. The first integrated circuit of claim 1 , where the receive equalizer comprises a partial response equalizer and where the specific symbol latency corresponds to a first post-cursor.

3. The first integrated circuit of claim 1 , where the transmit equalizer is operable to equalize intersymbol interference corresponding to a precursor to the main bit of the first data in the first mode, and is not operable to equalize intersymbol interference corresponding to the precursor to the main bit of the first data in the second mode.

4. The first integrated circuit of claim 3 , where the transmit equalizer includes a tap which is configured to compensate for precursor interference in the first mode, and which is configured to compensate for post-cursor interference in the second mode.

5. The first integrated circuit of claim 4 , where the receive equalizer includes a partial response decision feedback equalizer, where the partial response decision feedback equalizer is configured to compensate for first post-cursor interference in the first mode, where the partial response decision feedback equalizer is not configured to compensate for first post-cursor interference in second mode, and where the tap is configured to compensate for first post-cursor intersymbol interference in the second mode.

6. The first integrated circuit of claim 1 , where the transmitter is operable to receive parallel data, is operable to convert the parallel data into a sequence of bits, and is operable to consecutively transmit the sequence of bits to the second integrated circuit as a serial, differential output signal.

7. The first integrated circuit of claim 1 , where the transmitter is operable to receive ten-bit parallel data, is operable to convert the ten-bit parallel data into a sequence of bits, and is operable to consecutively transmit the sequence of bits to the second integrated circuit as a serial, differential output signal.

8. The first integrated circuit of claim 1 , where the receiver further comprises a linear equalizer to equalize the second data to produce an output signal, where the receive equalizer is operable to receive and equalize the output signal.

9. A first integrated circuit, comprising:
a transmitter having a transmit equalizer with at least one tap, the transmit equalizer operable to equalize first data to be transmitted to a second integrated circuit; and
a receiver having a receive equalizer with at least one tap, the receive equalizer operable to equalize second data to be received from the second integrated circuit;
where the first integrated circuit is operable to implement at least two different equalization modes, including
a first mode, in which the at least one tap of the transmit equalizer and the at least one tap of the receive equalizer are each operable to mitigate intersymbol interference arising from respective, different symbol latencies relative to a main bit of the first data and a main bit of the second data, respectively, and
a second mode, in which a tap of the at least one tap of the receive equalizer is disabled, such that it is not operable to not mitigate intersymbol interference, and in which a tap of the transmit equalizer is operable to mitigate intersymbol interference arising from a symbol latency mitigated by the receive equalizer in the first mode.

10. The first integrated circuit of claim 9 , where the tap disabled in the second mode includes a partial-response tap.

11. The first integrated circuit of claim 9 , where the receive equalizer includes a partial response decision feedback equalizer having plural sample paths, and where at least one sample path of the partial response decision feedback equalizer is disabled in the second mode.

12. The first integrated circuit of claim 9 , where the receive equalizer includes a decision feedback equalizer and where the tap disabled in the second mode includes a tap of the decision feedback equalizer.

13. The first integrated circuit of claim 12 , where the tap disabled in the second mode corresponds to a first post cursor, representing a symbol received immediately prior to the main bit of the second data.

14. The first integrated circuit of claim 9 , where:
the transmitter includes driver circuit having a plurality of driver input terminals;
the at least one tap of the transmit equalizer includes a plurality of taps coupled to respective ones of the driver input terminals, the plurality of taps including a main tap and an adjustable tap with a symbol latency relative to the main tap; and
circuitry supporting
the first mode, in which the circuitry is operable to adjust symbol latency addressed by the adjustable tap to a first symbol latency relative to the main tap, and
the second mode, in which the circuitry is operable to adjust symbol latency addressed by the adjustable tap to a second symbol latency relative to the main tap.

15. The first integrated circuit of claim 14 , where the first symbol latency represents a precursor symbol in the first mode and the second symbol latency represents a post-cursor symbol in the second mode.

16. The first integrated circuit of claim 9 , where the receiver further comprises a linear equalizer to equalize the second data to produce an output signal, where the receive equalizer is operable to receive and equalize the output signal.

17. The first integrated circuit of claim 16 , where the linear equalizer is enabled in the first mode and is disabled in one of the second mode or a third mode.

18. The first integrated circuit of claim 9 , where a tap of the at least one tap of the transmit equalizer is operable to compensate for precursor interference in the first mode and is not operable to compensate for precursor interference in at least one of the second mode or a third mode.

19. The first integrated circuit of claim 18 , where the tap operable to compensate for precursor interference in the first mode is configured in the second mode to compensate for post-cursor intersymbol interference.

20. The first integrated circuit of claim 18 , where the transmitter is operable to receive parallel data, is operable to convert the parallel data into a sequence of bits, and is operable to consecutively transmit the sequence of bits to the second integrated circuit as a serial, differential output signal.

21. The first integrated circuit of claim 9 , where the transmitter is operable to receive ten-bit parallel data, is operabl

Assignees

• Zerbe Jared L
• Chen Fred F
• Ho Andrew
• Farjad-Rad Ramin
• Poulton John W
• Donnelly Kevin S
• Leibowitz Brian
• Rambus Inc

Inventors

• Zerbe Jared L
• Chen Fred F
• Ho Andrew
• Farjad-Rad Ramin
• Poulton John W
• Donnelly Kevin S
• Leibowitz Brian

Classifications

• H04W52/225

  Calculation of statistics, e.g. average or variance · CPC title

• H04L1/0026 Primary

  Transmission of channel quality indication · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03343

  Arrangements at the transmitter end · CPC title