Memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11515474-B2
Application number	US-202017112861-A
Country	US
Kind code	B2
Filing date	Dec 4, 2020
Priority date	Nov 22, 2017
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

First claim

What is claimed is:

1. A memory device, comprising:
a semiconductor substrate;
a first dielectric layer over the semiconductor substrate;
a metal contact passing through the first dielectric layer;
an aluminum nitride layer extending along a top surface of the first dielectric layer and a top surface of the metal contact;
an aluminum oxide layer extending along a top surface of the aluminum nitride layer;
a second dielectric layer over the aluminum oxide layer;
a metal via passing through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and landing on the metal contact; and
a memory stack landing on the metal via.

2. The memory device of claim 1 , wherein the aluminum nitride layer has a thickness in a range from about 5 Å to about 100 Å.

3. The memory device of claim 1 , wherein the aluminum nitride layer has a thinner thickness than the aluminum oxide layer.

4. The memory device of claim 1 , wherein a ratio of a thickness of the aluminum oxide layer to a thickness of the aluminum nitride layer is in a range from about 1 to about 10.

5. The memory device of claim 1 , wherein a thickness of a combination of the aluminum nitride layer and the aluminum oxide layer is less than about 1100 Å.

6. The memory device of claim 1 , wherein a thickness of a combination of the aluminum nitride layer and the aluminum oxide layer is greater than about 10 Å.

7. The memory device of claim 1 , wherein an atomic percentage content of aluminum in the aluminum nitride layer is greater than an atomic percentage content of nitrogen in the aluminum nitride layer.

8. The memory device of claim 1 , wherein the second dielectric layer is made of tetra-ethyl-ortho-silicate.

9. The memory device of claim 1 , further comprising a transistor on the semiconductor substrate, wherein the metal contact is in contact with a source/drain structure of the transistor.

10. The memory device of claim 1 , wherein the memory stack comprises:
a bottom electrode layer;
a storage layer over the bottom electrode layer, wherein a sidewall of the storage layer is coterminous with a sidewall of the bottom electrode layer; and
a top electrode layer over the storage layer.

11. A memory device, comprising:
a transistor;
a first dielectric layer over the transistor;
a metal contact passing through the first dielectric layer;
an etch stop layer extending along a top surface of the first dielectric layer and spanning the metal contact;
a second dielectric layer over the etch stop layer;
a metal via passing through the second dielectric layer and the etch stop layer and landing on the metal contact; and
a memory stack landing on the metal via, wherein a first portion of the second dielectric layer overlapping the memory stack has a thicker thickness than a second portion of the second dielectric layer non-overlapping the memory stack.

12. The memory device of claim 11 , wherein the metal via has a top surface higher than the second portion of the second dielectric layer non-overlapping by the memory stack.

13. The memory device of claim 11 , wherein the metal via has a top surface level with a top surface of the first portion of the second dielectric layer overlapping by the memory stack.

14. The memory device of claim 11 , further comprising a spacer laterally surrounding the memory stack, wherein the spacer has a lower bottommost end than the memory stack.

15. The memory device of claim 11 , further comprising a spacer laterally surrounding the memory stack, wherein a bottommost end of the spacer is lower than a topmost end of the metal via.

16. The memory device of claim 11 , further comprising a metal nitride layer sandwiched between the etch stop layer and the first dielectric layer, wherein the etch stop layer is made of metal oxide, and the etch stop layer has a thicker thickness than the metal nitride layer.

17. A method for manufacturing a memory device, comprising:
forming a contact in a first dielectric layer;
forming a plurality of amine groups on a top surface of the contact and a top surface of the first dielectric layer;
after forming the plurality of amine groups, introducing an aluminum-containing precursor to the contact and the first dielectric layer to form an aluminum nitride layer extending along the top surface of the contact and the top surface of the first dielectric layer;
forming an etch stop layer over the aluminum nitride layer;
forming a second dielectric layer over the etch stop layer;
etching the second dielectric layer to form a through hole and stopping the etching at the etch stop layer;
after forming the through hole, etching the etch stop layer and the aluminum nitride layer via the through hole to expose the contact;
filling the through hole with a conductive material to form a metal via land on the contact; and
forming a memory stack on the metal via.

18. The method of claim 17 , wherein introducing the aluminum-containing precursor to the contact and the first dielectric layer to form the aluminum nitride layer includes replacing a plurality of hydrogen atoms in the amine groups with the aluminum-containing precursor.

19. The method of claim 17 , wherein the aluminum-containing precursor comprises AlN(CH 3 ) 2 .

20. The method of claim 17 , wherein etching the etch stop layer and the aluminum nitride layer is performed by a wet etching process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Jung-Tang
• Tung Szu-Ping
• Wu Szu-Hua
• Pan Shing-Chyang
• Wu Meng-Yu

Classifications

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title