High breakdown voltage structure for high performance GaN-based HEMT and MOS devices to enable GaN C-MOS

Patent metadata

Field	Value
Publication number	US-11515407-B2
Application number	US-201816232535-A
Country	US
Kind code	B2
Filing date	Dec 26, 2018
Priority date	Dec 26, 2018
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack is located over over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm;
a back barrier in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al; and
a polarization stack over the relaxed buffer stack.

2. The integrated circuit structure of claim 1 , wherein the back barrier is approximately 0.75-1.25 μm in thickness.

3. The integrated circuit structure of claim 1 , wherein the group III-N semiconductor material comprises GaN.

4. The integrated circuit structure of claim 1 , wherein the relaxed buffer stack further comprises a bottom material layer of aluminum and nitrogen, and the plurality of AlGaN material layers are over the bottom material layer.

5. The integrated circuit structure of claim 1 , wherein the plurality of AlGaN material layers each have a thickness less than approximately 250 nm and have a decreasing percentage of Al from a bottom one of the plurality of AlGaN material layers to a top one of the plurality of AlGaN material layers.

6. The integrated circuit structure of claim 5 , wherein the plurality of AlGaN material layers include a first AlGaN material layer on the bottom material layer, a second AlGaN material layer on the first AlGaN material layer, and a third AlGaN material layer on the second AlGaN material layer.

7. The integrated circuit structure of claim 6 , wherein the first AlGaN material layer comprises approximately 75% Al, the second AlGaN material layer comprises approximately 48% Al, and the third AlGaN material layer comprises approximately 25% Al.

8. The integrated circuit structure of claim 6 , wherein the first AlGaN material layer is approximately 75-125 nm in thickness, the second AlGaN material layer is approximately 175-225 nm in thickness, and the third AlGaN material layer is approximately 175-225 nm in thickness.

9. The integrated circuit structure of claim 1 , further comprising both an n-type device and a p-type device one-on the relaxed buffer stack, wherein the n-type device comprises the buffer stack on the relaxed buffer stack and the polarization stack on the buffer stack; and the p-type device comprises the buffer stack on the relaxed buffer stack.

10. The integrated circuit structure of claim 9 , wherein the n-type device includes a two-dimensional electron gas (2 DEG) configuration at an interface between an interlayer of the polarization stack and the buffer stack; and wherein the p-type device includes a two-dimensional hole gas (2DHG) configuration at an interface of the buffer stack and the back barrier.

11. The integrated circuit structure of claim 1 , wherein the channel region comprises one of an enhancement mode device and a depletion mode device.

12. The integrated circuit structure of claim 1 , further comprising a cap layer over the polarization stack.

13. The integrated circuit structure of claim 12 , wherein the cap layer comprises at least one of SiNx, SiO 2 , and BN.

14. A transistor, comprising:
a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region comprise GaN, wherein the relaxed buffer stack comprises: a bottom material layer, a plurality of AlGaN material layers over the bottom material layer, and a buffer stack over the plurality of AlGaN material layers, wherein the buffer stack comprises GaN and has a thickness of less than approximately 25 nm;
a back barrier in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al;
a polarization stack over the relaxed buffer stack; and
source and drain regions adjacent to the channel region.

15. The transistor of claim 14 , wherein the back barrier is approximately 0.75-1.25 μm in thickness.

16. The transistor of claim 14 , wherein the plurality of AlGaN material layers each have a thickness less than approximately 250 nm and have a decreasing percentage of Al from a bottom one of the plurality of AlGaN material layers to a top one of the plurality of AlGaN material layers.

17. The transistor of claim 16 , wherein the plurality of AlGaN material layers include a first AlGaN material layer on the bottom material layer, a second AlGaN material layer on the first AlGaN material layer, and a third AlGaN material layer on the second AlGaN material layer, wherein the first AlGaN material layer comprises approximately 75% Al, the second AlGaN material layer comprises approximately 48% Al, and the third AlGaN material layer comprises approximately 25% Al.

18. The transistor of claim 17 , wherein the first AlGaN material layer is approximately 75-125 nm in thickness, the second AlGaN material layer is approximately 175-225 nm in thickness, and the third AlGaN material layer is approximately 175-225 nm in thickness.

19. The transistor of claim 14 , further comprising both an n-type device and a p-type device one on the relaxed buffer stack, wherein the n-type device comprises the buffer stack on the relaxed buffer stack and the polarization stack on the buffer stack; and the p-type device comprises the buffer stack on the relaxed buffer stack.

20. The transistor of claim 19 , wherein the n-type device includes a two-dimensional electron gas (2 DEG) configuration at an interface between an interlayer of the polarization stack and the buffer stack; and wherein the p-type device includes a two-dimensional hole gas (2DHG) configuration at an interface of the buffer stack and the back barrier.

21. The transistor of claim 14 , wherein the channel region comprises one of an enhancement mode device and a depletion mode device.

22. The transistor of claim 14 , further comprising a cap layer over the polarization stack.

23. The transistor of claim 22 , wherein the cap layer comprises at least one of SiNx, SiO 2 , and BN.

Assignees

• Intel Corp

Inventors

• Glass Glenn
• Dasgupta Sansaptak
• Then Han Wui
• Radosavljevic Marko
• Fischer Paul
• Murthy Anand
• Hafez Walid

Classifications

• H10P50/646

  of Group III-V materials · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title