Method for processing a semiconductor wafer, semiconductor composite structure and support structure for semiconductor wafer

US11515264B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11515264-B2
Application numberUS-201916421707-A
CountryUS
Kind codeB2
Filing dateMay 24, 2019
Priority dateMay 25, 2018
Publication dateNov 29, 2022
Grant dateNov 29, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for processing a semiconductor wafer, the method comprising: welding at least one support structure onto the semiconductor wafer; and reducing a thickness of the semiconductor wafer before or after welding the at least one support structure onto the semiconductor wafer. 2. The method of claim 1 , wherein welding the at least one support structure onto the semiconductor wafer comprises: placing the at least one support structure on the semiconductor wafer; and irradiating light through the at least one support structure or through the semiconductor wafer to form a weld region, wherein the weld region is an interface between the at least one support structure and the semiconductor wafer, and/or a joining structure between the at least one support structure and the semiconductor wafer. 3. The method of claim 2 , wherein light of a first wavelength is irradiated through the at least one support structure, and wherein at least 50% of the light of the first wavelength impinging on the support structure is transmitted through the support structure and reaches the weld region. 4. The method of claim 1 , further comprising: before welding the at least one support structure, forming an absorption region on the semiconductor wafer or on the at least one support structure. 5. The method of claim 4 , wherein the absorption region comprises a silicide layer. 6. The method of claim 5 , wherein the silicide layer is a nickel silicide layer, a cobalt silicide layer or a titanium silicide layer. 7. The method of claim 4 , wherein the absorption region comprises a polysilicon layer or an amorphous silicon layer. 8. The method of claim 4 , wherein forming the absorption region comprises implanting ions so that the absorption region comprises a doping concentration of at least 1·10 19 cm 3 . 9. The method of claim 4 , further comprising: before reducing the thickness of the semiconductor wafer, forming an electrical element structure of a semiconductor device at a front side of the semiconductor wafer, wherein forming the electrical element structure comprises of forming a polycrystalline silicon layer and/or forming a metallization layer, wherein the absorption region comprises a part of the polycrystalline silicon layer and/or the metallization layer. 10. The method of claim 1 , wherein the at least one support structure comprises a ring structure or a grid structure. 11. The method of claim 1 , wherein the at least one support structure comprises at least one ring segment structure and/or at least one circular structure. 12. The method of claim 1 , wherein the at least one support structure is welded to a front side of the semiconductor wafer, and wherein the method further comprises: before reducing the thickness of the semiconductor wafer, placing a carrier structure at the front side of the semiconductor wafer. 13. The method of claim 12 , further comprising: before placing the carrier structure at the front side, filling a gap between the semiconductor wafer and the carrier structure with foam material. 14. The method of 12 , further comprising: after reducing the thickness of the semiconductor wafer, removing the carrier structure. 15. The method of claim 1 , further comprising: after welding the at least one support structure onto the semiconductor wafer, processing the semiconductor wafer at a temperature of at least 400° C.

Assignees

Inventors

Classifications

  • Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) · CPC title

  • H10W42/121Primary

    protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

  • Electricity · mapped topic

  • H01L23/562Primary

    Electricity · mapped topic

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Frequently asked questions

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What does patent US11515264B2 cover?
A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the fi…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W42/121. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 29 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).