Erasing memory

Patent metadata

Field	Value
Publication number	US-11514987-B2
Application number	US-202117228807-A
Country	US
Kind code	B2
Filing date	Apr 13, 2021
Priority date	Aug 29, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

First claim

What is claimed is:

1. A method of operating a memory, comprising:
during an operation to erase a memory cell of a string of series-connected memory cells of the memory:
applying a first voltage signal having a first voltage level to a first node selectively connected to the string of series-connected memory cells while applying a second voltage signal having a second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells; and
increasing the first voltage signal applied to the first node to a third voltage level while increasing the second voltage signal applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level;
wherein the first voltage level is a positive voltage level; and
wherein the second voltage level is a negative voltage level.

2. The method of claim 1 , further comprising:
while the first voltage signal applied to the first node is at the third voltage level, applying a third voltage signal to a control gate of the memory cell having a particular voltage level that is expected to remove charge from a data storage structure of the memory cell.

3. The method of claim 2 , further comprising applying the third voltage signal having the particular voltage level to the control gate of the memory cell before increasing the first voltage signal applied to the first node to the third voltage level.

4. The method of claim 1 , wherein a voltage difference between the first voltage level and the second voltage level is equal to a voltage difference between the third voltage level and the fourth voltage level.

5. The method of claim 4 , wherein the voltage difference between the first voltage level and the second voltage level is equal to a voltage difference sufficient to generate gate-induced drain leakage (GIDL) current through the transistor.

6. The method of claim 4 , wherein increasing the first voltage signal applied to the first node to the third voltage level has a particular duration, and wherein increasing the second voltage signal applied to the control gate of the transistor to the fourth voltage level has the particular duration.

7. The method of claim 1 , wherein increasing the first voltage signal applied to the first node and increasing the second voltage signal applied to the control gate of the transistor comprises increasing the first voltage signal applied to the first node at a particular rate and increasing the second voltage signal applied to the control gate of the transistor at the particular rate.

8. The method of claim 7 , wherein increasing the first voltage signal applied to the first node at the particular rate and increasing the second voltage signal applied to the control gate of the transistor at the particular rate further comprises increasing the first voltage signal applied to the first node and increasing the second voltage signal applied to the control gate of the transistor at a variable rate.

9. The method of claim 1 , wherein increasing the first voltage signal applied to the first node to the third voltage level comprises increasing the first voltage signal applied to the first node to the third voltage level using a first plurality of step changes in voltage level, and wherein increasing the second voltage signal applied to the control gate of the transistor to the fourth voltage level comprises increasing the second voltage signal applied to the control gate of the transistor to the fourth voltage level using a second plurality of step changes in voltage level having a greater number of step changes in voltage level than the first plurality of step changes in voltage level.

10. The method of claim 1 , wherein the transistor is a first transistor, the method further comprising:
applying a third voltage signal having a fifth voltage level to a second node selectively connected to the string of series-connected memory cells while applying a fourth voltage signal having a sixth voltage level to a control gate of a second transistor connected between the second node and the string of series-connected memory cells; and
increasing the third voltage signal applied to the second node to a seventh voltage level while increasing the fourth voltage signal applied to the control gate of the second transistor connected to the second node to an eighth voltage level lower than the seventh voltage level and higher than the fifth voltage level;
wherein the fifth voltage level is a positive voltage level; and
wherein the sixth voltage level is a negative voltage level.

11. The method of claim 10 , wherein the fifth voltage level equals the first voltage level, the sixth voltage level equals the second voltage level, the seventh voltage level equals the third voltage level, and the eighth voltage level equals the fourth voltage level.

12. A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to perform a method comprising:
during an operation to erase a memory cell of a string of series-connected memory cells of die plurality of stings of series-connected memory cells:
applying a first voltage signal having first voltage level to a first node selectively connected to the string of series-connected memory cells while applying a second voltage signal having a second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells; and
increasing the first voltage signal applied to the first node to a third voltage level while increasing the second voltage signal applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level;
wherein the first voltage level is a positive voltage level; and
wherein the second voltage level is a negative voltage level.

13. The memory of claim 12 , wherein the controller is configured to cause the memory to perform the method further comprising:
while the first voltage signal applied to the first node is at the third voltage level, applying a third voltage signal to a control gate of the memory cell having a particular voltage level that is expected to remove charge from a data storage structure of the memory cell.

14. The memory of claim 13 , wherein the controller is configured to cause the memory to perform the method further comprising:
applying the third voltage signal having the particular voltage level to the control gate of the memory cell before increasing the first voltage signal applied to the first node to the third voltage level.

15. The memory of claim 12 , wherein a voltage difference between the first voltage level and the second voltage level is equal to a voltage difference between the third voltage level and the fourth voltage level.

16. The memory of claim 15 , wherein the voltage difference between the first voltage level and the second voltage level is equal to a voltage difference sufficient to generate gate-induced drain leakage (GIDL) current through the transistor.

17. The memory of claim 15 , wherein increasing the first voltage signal applied to the first node to the third voltage level has a particular duration, and wherein increasing the second voltage signal applied to the control gate of the transistor to the fourth voltage level has the particular duration.

18. The memory of claim

Assignees

• Micron Technology Inc

Inventors

• Paolucci Giovanni Maria
• Tessariol Paolo
• Camerlenghi Emilio
• Carnevale Gianpietro
• Benvenuti Augusto

Classifications

• G11C16/30

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• G11C16/32

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• G11C16/24

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• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title