Erasing memory

Patent metadata

Field	Value
Publication number	US-11011236-B2
Application number	US-201916555050-A
Country	US
Kind code	B2
Filing date	Aug 29, 2019
Priority date	Aug 29, 2019
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

First claim

What is claimed is:

1. A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
apply a first voltage signal having a first voltage level to a first node selectively connected to a string of series-connected memory cells of the plurality of strings of memory cells while applying a second voltage signal having the first voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells;
increase the first voltage signal applied to the first node to a second voltage level while decreasing the second voltage signal applied to the control gate of the transistor to a third voltage level; and
for each time period of a plurality of successive time periods:
increase the first voltage signal applied to the first node by a corresponding magnitude for that time period; and
increase the second voltage signal applied to the control gate of the transistor by the corresponding magnitude for that time period.

2. The memory of claim 1 , wherein the controller is further configured to cause the memory to:
after a last time period of the plurality of successive time periods, apply a third voltage signal to a control gate of a memory cell of the string of series-connected memory cells having a voltage level expected to remove charge from a data storage structure of the memory cell.

3. The memory of claim 1 , wherein the controller being configured to cause the memory to apply the first voltage level to the first node comprises the controller being configured to cause the memory to apply the first voltage level to a node selected from a group consisting of a source selectively connected to the string of series-connected memory cells and a data line selectively connected to the string of series-connected memory cells.

4. The memory of claim 1 , wherein the controller being configured to cause the memory to apply the first voltage level to the first node further comprises the controller being configured to cause the memory to apply a ground voltage to the first node.

5. The memory of claim 1 , wherein a voltage difference between the second voltage level and the third voltage level is configured to generate gate-induced drain leakage (GIDL) current through the transistor from the first node.

6. The memory of claim 1 , wherein the corresponding magnitude for a particular time period of the plurality of successive time periods is greater than the corresponding magnitude for a different time period of the plurality of successive time periods.

7. The memory of claim 6 , wherein the particular time period is a first time period of the plurality of successive time periods.

8. The memory of claim 7 , wherein the corresponding magnitude for each time period of the plurality of successive time periods other than the particular time period are a same magnitude.

9. A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
apply a first voltage signal having a first voltage level to a source selectively connected to a string of series-connected memory cells of the plurality of strings of memory cells while applying a second voltage signal having the first voltage level to a control gate of a transistor connected between the source and the string of series-connected memory cells;
increase the first voltage signal applied to the source to a positive second voltage level while decreasing the second voltage signal applied to the control gate of the transistor to a negative third voltage level; and
for each time period of a plurality of successive time periods:
increase the first voltage signal applied to the source by a corresponding magnitude for that time period; and
increase the second voltage signal applied to the control gate of the transistor by the corresponding magnitude for that time period; and

after a last time period of the plurality of successive time periods, apply a third voltage signal to a control gate of a memory cell of the string of series-connected memory cells having a voltage level expected to remove charge from a data storage structure of the memory cell.

10. The memory of claim 9 , wherein the controller being configured to cause the memory to apply the third voltage signal to the control gate of the memory cell after the last time period of the plurality of successive time periods comprises the controller being further configured to cause the memory to apply the third voltage signal to the control gate of the memory cell before an initial time period of the plurality of successive time periods.

11. The memory of claim 9 , wherein a voltage difference between the positive second voltage level and the negative third voltage level is equal to a voltage difference sufficient to generate gate-induced drain leakage (GIDL) current through the transistor.

12. The memory of claim 9 , wherein each time period of the plurality of time periods has a corresponding slope of a voltage increase for that time period, and wherein the corresponding slope of the voltage increase for a particular time period of the plurality of time periods is equal to the corresponding slope of the voltage increase for each remaining time period of the plurality of time periods.

13. The memory of claim 9 , wherein the transistor is a first transistor, and wherein the controller is further configured to cause the memory to:
apply a fourth voltage signal having the first voltage level to a data line selectively connected to the string of series-connected memory cells while applying a fifth voltage signal having the first voltage level to a control gate of a second transistor connected between the data line and the string of series-connected memory cells;
increase the fourth voltage signal applied to the data line to the positive second voltage level while decreasing the fifth voltage signal applied to the control gate of the second transistor to the negative third voltage level; and
for each time period of the plurality of successive time periods:
increase the fourth voltage signal applied to the data line by the corresponding magnitude for that time period; and
increase the fifth voltage signal applied to the control gate of the second transistor by the corresponding magnitude for that time period.

14. A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
apply a first voltage signal having a first voltage level to a source selectively connected to a string of series-connected memory cells of the plurality of strings of memory cells and apply a second voltage signal having the first voltage level to a data line selectively connected to a different end of the string of series-connected memory cells opposite the one end while applying a third voltage signal having the first voltage level to a control gate of a first transistor connected between the source and one end of the string of series-connected memory cells and while applying a fourth voltage signal having the first voltage level to a control gate of a second transistor connected between the data line and different end of the string of series-connected memory cells;
increase the first voltage signal applied to the source to a

Assignees

• Micron Technology Inc

Inventors

• Paolucci Giovanni Maria
• Tessariol Paolo
• Camerlenghi Emilio
• Carnevale Gianpietro
• Benvenuti Augusto

Classifications

• G11C16/14 Primary

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• G11C16/16 Primary

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• G11C16/32

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• G11C16/24

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• G11C16/30

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