Methods including establishing a negative body potential in a memory cell

Patent metadata

Field	Value
Publication number	US-10049750-B2
Application number	US-201615350229-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	Nov 14, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.

First claim

What is claimed is:

1. A method of operating a memory, comprising:
establishing a negative potential in a body of a memory cell, the memory cell comprising a data storage structure electrically isolated from the body; and
initiating a sensing operation on the memory cell.

2. The method of claim 1 , further comprising receiving a command from an external device indicating a desire to establish the negative potential in the body of the memory cell.

3. The method of claim 2 , wherein initiating the sensing operation on the memory cell occurs while the body of the memory cell has the negative potential.

4. The method of claim 1 , wherein establishing the negative potential in the body of the memory cell comprises applying a negative voltage level to a source connected to the body of the memory cell.

5. The method of claim 1 , wherein the memory cell is a particular memory cell of a string of series-connected memory cells, and wherein establishing the negative potential in the body of the memory cell comprises applying a same positive voltage level to each access line of a plurality of access lines, where each access line of the plurality of access lines is connected to a respective memory cell of the string of series-connected memory cells.

6. The method of claim 1 , further comprising:
advancing a timer; and
establishing the negative potential in the body of the memory cell in response to a value of the timer having a desired value.

7. The method of claim 6 , wherein the timer is configured to output a count value, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to the count value having the desired value.

8. The method of claim 7 , further comprising:
resetting the timer to an initial value.

9. The method of claim 7 , further comprising:
modifying the desired value of the timer in response to an indication of temperature.

10. The method of claim 6 , wherein the timer is configured to toggle a logic level of an output signal at intervals of some particular elapsed time, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to the output signal having a particular logic level.

11. The method of claim 10 , further comprising:
modifying a length of the intervals in response to an indication of temperature.

12. A method of operating a memory, comprising:
advancing a timer; and
establishing a negative potential in a body of a memory cell in response to a value of the timer having a desired value, the memory cell comprising a data storage structure electrically isolated from the body; and
initiating a sensing operation on the memory cell while the body of the memory cell has the negative potential.

13. The method of claim 12 , wherein the timer is external to the memory, and wherein establishing the negative potential in the body of the memory cell is performed in response to a command received by the memory from a device external to the memory that is in communication with the timer.

14. The method of claim 12 , wherein the timer comprises a counter responsive to a clock signal, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to a count value of the counter having the desired value.

15. The method of claim 14 , further comprising:
resetting the counter to an initial value after the count value has the desired value.

16. The method of claim 14 , further comprising:
modifying the desired value of the count value in response to a temperature sensor indicating a temperature higher than a predefined upper threshold or lower than a predefined lower threshold.

17. The method of claim 12 , wherein the timer is configured to periodically toggle a logic level of an output signal from a first logic level to a second logic level at intervals of some particular elapsed time, and wherein establishing the negative potential in the body of the memory cell comprises establishing the negative potential in the body of the memory cell in response to the output signal having the second logic level.

18. The method of claim 17 , further comprising:
increasing a length of the intervals in response to a temperature sensor indicating a temperature higher than a predefined upper threshold; and
decreasing a length of the intervals in response to a temperature sensor indicating a temperature lower than a predefined lower threshold.

19. The method of claim 11 , wherein modifying the length of the intervals in response to the indication of temperature comprises increasing the length of the intervals in response to the indication of temperature being higher than a predefined upper threshold, and decreasing the length of the intervals in response to the indication of temperature being lower than a predefined lower threshold.

20. A method of operating a memory, comprising:
establishing a negative potential in a body of a memory cell, the memory cell comprising a data storage structure electrically isolated from the body; and
initiating a sensing operation on the memory cell while the body of the memory cell has the negative potential;
wherein the memory cell and a different memory cell are each selectively connected to a common source; and
wherein establishing the negative potential in the body of the memory cell is performed in response to an erase operation on the different memory cell.

Assignees

• Micron Technology Inc

Inventors

• Sakui Koji
• Hawes Mark
• Tanzawa Toru
• Binfet Jeremy

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title