Memory device and method having a control circuit configured to acquire information on a state of a control target, causes the control target to execute a read and write operation based on the state

Patent metadata

Field	Value
Publication number	US-11514970-B2
Application number	US-202117470802-A
Country	US
Kind code	B2
Filing date	Sep 9, 2021
Priority date	Feb 17, 2021
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.

First claim

The invention claimed is:

1. A memory device comprising:
a plurality of first interconnects;
a plurality of second interconnects each intersecting the first interconnects;
a plurality of first memory cells respectively provided at a plurality of intersections between the first interconnects and the second interconnects,
each of the first memory cells being coupled to one first interconnect of the first interconnects and one second interconnect of the second interconnects; and
a control circuit configured to:
acquire information on a state of a control target;
cause the control target to execute an action based on the state; and
execute a read operation and a write operation, based on the state, wherein
the control circuit is configured to execute a plurality of trial processes each including a first operation, a second operation and a third operation,
in the first operation, the control circuit executes a first read operation for a plurality of first memory cells coupled between a first interconnect selected from the first interconnects, based on the control target being in a first state, and the second interconnects, and selects a second interconnect, based on magnitudes of read currents of the second interconnects acquired by the first read operation,
in the second operation, the control circuit causes the control target to execute an action associated with the selected second interconnect, and the control target transitions to a second state after executing the action associated with the selected second interconnect,
in the third operation, the control circuit executes a first process or a second process in which the selected first interconnect is targeted, based on the control target being in the second state,
in the first process, the control circuit applies a write voltage of a first direction to a first memory cell coupled to the selected first interconnect and the selected second interconnect, and applies a write voltage of a second direction different from the first direction to a first memory cell coupled to the selected first interconnect and a non-selected second interconnect,
in second processes of first to m-th trial processes (m is an integer of 2 or more), the control circuit applies the write voltage of the second direction to the first memory cell coupled to the selected first interconnect and the selected second interconnect, and omits a write operation in which the first memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted, and
in second processes of (m+1)th and subsequent trial processes, the control circuit applies the write voltage of the second direction to the first memory cell coupled to the selected first interconnect and the selected second interconnect, and applies the write voltage of the first direction to the first memory cell coupled to the selected first interconnect and the non-selected second interconnect.

2. The device of claim 1 , further comprising:
a third interconnect that intersects the first interconnects;
a plurality of second memory cells respectively provided at a plurality of intersections between the first interconnects and the third interconnect, each of the second memory cells being coupled to one first interconnect of the first interconnects and the third interconnect; and
a memory circuit configured to store information on the trial processes, wherein
each of the trial processes includes a second read operation in which the second memory cells are targeted, and
the control circuit causes the memory circuit to store a sum of read currents of the second memory cells acquired by the second read operation as a first reference value.

3. The device of claim 2 , wherein
in the trial processes, where the control circuit detects that a first reference value acquired by an n-th trial process (n is an integer of 2 or more) is lower than a first reference value acquired by an (n−1)th trial process, the second processes of the (m+1)th and subsequent trial processes are executed in the second processes of (n+1)th and subsequent trial processes.

4. The device of claim 1 , wherein
in the first read operation, the control circuit is configured to:
apply a first voltage to the selected first interconnect;
apply a second voltage lower than the first voltage to a non-selected first interconnect; and
apply the second voltage to the second interconnects.

5. The device of claim 2 , wherein
in the second read operation, the control circuit is configured to:
apply a third voltage to the first interconnects; and
apply a fourth voltage lower than the third voltage to the third interconnect.

6. The device of claim 1 , wherein
where a write voltage of the first direction is applied to the first memory cell coupled to the selected first interconnect and the selected second interconnect, the control circuit is configured to:
apply a fifth voltage to the selected first interconnect;
apply a sixth voltage lower than the fifth voltage to the selected second interconnect; and
apply a seventh voltage intermediate between the fifth voltage and the sixth voltage to each of a non-selected first interconnect and the non-selected second interconnect, and
where the write voltage of the second direction is applied to the first memory cell coupled to the selected first interconnect and the selected second interconnect, the control circuit is configured to:
apply an eighth voltage to the selected first interconnect;
apply a ninth voltage higher than the eighth voltage to the selected second interconnect; and
apply a tenth voltage intermediate between the eighth voltage and the ninth voltage to each of the non-selected first interconnect and the non-selected second interconnect.

7. The device of claim 1 , further comprising:
a third interconnect intersecting the first interconnects;
a plurality of second memory cells respectively provided at a plurality of intersections between the first interconnects and the third interconnect, each of the second memory cells being coupled to one first interconnect of the first interconnects and the third interconnect; and
a memory circuit configured to store information on the trial processes, wherein
each of the trial processes includes a third read operation in which a second memory cell coupled to the selected first interconnect is targeted, and
the control circuit causes the memory circuit to store a read current value of the second memory cell acquired by the third read operation as a second reference value for each first interconnect.

8. The device of claim 7 , wherein
in a trial process in which the second reference value associated with the selected first interconnect decreases two or more times in a row, the control circuit omits the first process and the second process.

9. The device of claim 1 , further comprising:
a fourth interconnect intersecting the first interconnects; and
a plurality of third memory cells respectively provided at a plurality of intersections between the first interconnects and the fourth interconnect, each of the third memory cells being coupled to one first interconnect of the first interconnects and the fourth interconnect, wherein
after the trial processes are completed and where one first interconnect and one second interconnect are associated with each other, the control circuit executes a write operation including a verify operation, to a third memory cell coupled to the one first interconnect being targeted.

10. The device of claim 9 , further comprising:
a memory circuit configured to store information on the trial processes, wherein
after the trial processes, the control circuit executes a fourth read operation

Assignees

• Kioxia Corp

Inventors

• Yamaguchi Marina
• Ota Kensuke
• Yamamoto Kazuhiko
• Saitoh Masumi

Classifications

• G06N3/065

  Analogue means · CPC title

• G06N3/08

  Learning methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title