Pre-programmed resistive cross-point array for neural network

Patent metadata

Field	Value
Publication number	US-9659249-B1
Application number	US-201615277264-A
Country	US
Kind code	B1
Filing date	Sep 27, 2016
Priority date	Sep 27, 2016
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

Technical solutions are described for forming a semiconductor device for a crosspoint array that implements a pre-programmed neural network. An example method includes sequentially depositing a semiconducting layer, a top insulating layer, and a shunting layer onto a base insulating layer. The method further includes etching selective portions of the top insulating layer corresponding to resistance values associated with weights of the crossbar that implements the neural network.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
sequentially depositing a semiconducting layer, a top insulating layer, and a shunting layer onto a base insulating layer; and
etching selective portions of the top insulating layer corresponding to resistance values associated with weights of a crossbar that implements a neural network.

2. The method of claim 1 , further comprising etching selective portions of the shunting layer.

3. The method of claim 1 , wherein the insulating layer comprises a dielectric material that is selected from a group consisting of aluminum oxide (Al 2 O 3 ), magnesium oxide (MgO), boron nitride (BN), silicon oxynitride (SiO x N y ), and silicon oxide (SiO 2 ).

4. The method of claim 1 , wherein the shunting layer is deposited by using a self-aligned configuration, wherein the shunting layer comprises shunting material that reacts with semiconducting material of the semiconducting layer.

5. The method of claim 4 , wherein the shunting material reacts with the semiconducting material in response to applying heat.

6. The method of claim 4 , wherein the shunting material is selected from a group consisting of silicides of titanium, nickel, cobalt, and platinum, and germanides of titanium, nickel, cobalt, and platinum.

7. The method of claim 1 , wherein the shunting layer is deposited in a patterned manner by using a lithographic process.

8. A method for fabricating a semiconductor device for a crosspoint device from a crosspoint array, the method comprising:
depositing a semiconducting layer on a base insulating layer;
depositing a top insulating layer on the semiconducting layer;
removing a portion of the top insulating layer; and
depositing a shunting layer on the top insulating layer, wherein the shunting layer contacts the semiconducting layer via the portion that is removed from the top insulating layer, wherein the dimensions of the portion determine a resistance value of the crosspoint device.

9. The method of claim 8 , further comprising etching a selective portion of the shunting layer, wherein the selective portion that is etched from the shunting layer is associated with the portion removed from the insulating layer.

10. The method of claim 9 , wherein the insulating layer comprises a dielectric material that is selected from a group consisting of aluminum oxide (Al 2 O 3 ), magnesium oxide (MgO), boron nitride (BN), silicon oxynitride (SiO x N y ), and silicon oxide (SiO 2 ).

11. The method of claim 9 , wherein the shunting layer is deposited by using a self-aligned configuration, wherein the shunting layer comprises shunting material that reacts with semiconducting material of the semiconducting layer.

12. The method of claim 11 , wherein the shunting material reacts with the semiconducting material in response to applying heat.

13. The method of claim 8 , wherein the shunting material is selected from a group consisting of silicides of titanium, nickel, cobalt, and platinum, and germanides of titanium, nickel, cobalt, and platinum.

14. The method of claim 8 , wherein the shunting layer is deposited in a patterned manner by using a lithographic process.

Assignees

• IBM

Inventors

• Copel Matthew W

Classifications

• G06N3/065 Primary

  Analogue means · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• G06N3/0635 Primary

  Physics · mapped topic

• G06N3/08

  Learning methods · CPC title

• H01L27/2463

  Electricity · mapped topic