Automation for monolithic 3D devices

Patent metadata

Field	Value
Publication number	US-10127344-B2
Application number	US-201514672202-A
Country	US
Kind code	B2
Filing date	Mar 29, 2015
Priority date	Apr 15, 2013
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a first strata and a second strata; then performing a first placement of the first strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of the second strata based on the first placement, where the partitioning includes a partition between logic and memory, and where the logic includes at least one decoder representation for the memory.

First claim

We claim:

1. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a first strata and a second strata; then
performing a first placement of said first strata using a 2D placer executed by a computer,
wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and

performing a second placement of said second strata based on said first placement,
wherein said partitioning comprises a partition between logic and memory,
wherein said logic comprises at least one decoder representation for said memory,
wherein said at least one decoder representation has a virtual size with width of contacts for through silicon vias,
wherein said performing a first placement comprises using said decoder representation instead of an actual memory decoder, and
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.

2. The method according to claim 1 , further comprising:
performing routing for first routing layers overlaying said first strata, second routing layers overlying said second strata, and through silicon vias connecting said first routing layers and said second routing layers.

3. The method according to claim 1 ,
wherein said performing placement comprises placement of said at least one decoder representation for at least a portion of said memory, and
wherein the placement of said at least a portion of said memory is defined by the placement of said at least one decoder representation.

4. The method according to claim 1 ,
wherein said memory comprises at least a first memory and a second memory,
wherein said first memory comprises first memory decoder representations and said second memory comprises second memory decoder representations, and
wherein said 2D placer is set so said second memory decoder representations are not placed within a rectangle defined by the placement of said first memory decoder representations.

5. The method according to claim 1 ,
wherein said decoder representation is placed on said first strata, and
wherein an actual memory decoder and associated bit cells are placed on said second strata, and
wherein placement of said actual memory decoder and associated bit cells is based on said decoder representation placement.

6. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a first strata and a second strata; then
performing a first placement of said first strata using a 2D placer executed by a computer,
wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and

performing a second placement of said second strata based on said first placement,
wherein said partitioning comprises a partition between logic and memory,
wherein said logic comprises at least one decoder for said memory wherein said memory comprises at least a first memory and a second memory,
wherein said first memory comprises first memory decoders and said second memory comprises second memory decoders,
wherein said 2D placer is set so said second memory decoders are not placed within a rectangle defined by the placement of said first memory decoders, and
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.

7. The method according to claim 6 ,
wherein said second strata comprises mostly memory bit cells.

8. The method according to claim 6 ,
wherein performing a second placement comprises the use of said 2D placer.

9. The method according to claim 6 ,
wherein said at least one decoder has a virtual size with width of contacts for through silicon vias, and
wherein said performing a first placement comprises using a decoder representation of said decoder.

10. The method according to claim 6 , further comprising:
performing routing for first routing layers overlaying said first strata, second routing layers overlying said second strata, and through silicon vias connecting said first routing layers and said second routing layers.

11. The method according to claim 6 , further comprising:
performing a synthesis step using two libraries.

12. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a first strata and a second strata; then
performing a first placement of said first strata using a 2D placer executed by a computer,
wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and

performing a second placement of said second strata based on said first placement,
wherein said partitioning comprises a partition between logic and memory,
wherein said partition comprises a step of assigning at least one memory block to a logic strata for improved balancing of said logic strata area and a memory strata area, and
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.

13. The method according to claim 12 , further comprising:
performing routing for first routing layers overlaying said first strata, second routing layers overlying said second strata, and through silicon vias connecting said first routing layers and said second routing layers.

14. The method according to claim 12 ,
wherein said memory comprises at least a first memory and a second memory,
wherein said first memory comprises first memory decoder representations and said second memory comprises second memory decoder representations, and
wherein said 2D placer is set so said second memory decoder representations are not placed within a rectangle defined by the placement of said first memory decoder representations.

15. The method according to claim 12 ,
wherein said performing placement comprises placement of said at least one decoder representation for at least a portion of said memory, and
wherein the placement of said at least a portion of said memory is defined by the placement of said at least one decoder representation.

16. The method according to claim 12 ,
wherein said at least one decoder representation has a virtual size with width of contacts for through silicon vias, and
wherein said performing a first placement comprises using said decoder representation instead of an actual memory decoder.

17. The method according to claim 12 ,
wherein said logic comprises at least one decoder representation for said memory.

18. The method according to claim 12 ,
wherein said logic comprises at least one decoder for said memory.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Wurman Zeev

Classifications

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5077

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic