Back end of line process integrated optical device fabrication

US11506840B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11506840-B2
Application numberUS-201916398634-A
CountryUS
Kind codeB2
Filing dateApr 30, 2019
Priority dateJun 4, 2015
Publication dateNov 22, 2022
Grant dateNov 22, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.

First claim

Opening claim text (preview).

What is claimed is: 1. An optical device, comprising: a substrate; a silicon device layer on the substrate, the silicon device layer including at least one optical device; a vertical stack of metal layers being located over the silicon device layer and electrically connecting between external contacts and the silicon device layer; a vertical stack of silicon nitride layers, the metal layers being between the silicon nitride layers; and an optical coupler comprising portions of at least ene some of the silicon nitride layers, the optical coupler being for coupling light into or out of the silicon device layer. 2. The device according to claim 1 , further comprising: a first oxide layer on the silicon device layer, a first of the silicon nitride layers being on the first oxide layer; a second oxide layer on the first of the silicon nitride layers stop layer, the second oxide layer including a first of the metal layers therein, a second of the silicon nitride layers being on the second oxide layer; and a first metal via connecting the first of the metal layers to the silicon device layer. 3. The device according to claim 2 , wherein the optical coupler comprises a portion of the first of the silicon nitride layers, and a portion of the second of the silicon nitride layers. 4. The device according to claim 3 , wherein at least one of the silicon nitride layers comprises a tapered portion in the optical coupler. 5. The device according to claim 2 , further comprising: a third oxide layer on the second of the silicon nitride layers, a third of the silicon nitride layers being on the third oxide layer; and a fourth oxide layer on the third of the silicon nitride layers; wherein the optical coupler comprises a portion of the third of the silicon nitride layers; and wherein a second of the metal layers is in a first portion of the fourth oxide seventh layer; and further comprising a second metal via connecting the second of the metal layers to the silicon device layer. 6. The device according to claim 5 , wherein the third waveguide comprises an arrayed waveguide grating (AWG). 7. The device according to claim 6 , wherein the AWG is more than 4 micrometers from the device layer. 8. The device according to claim 5 , wherein the third waveguide comprises a multimode interference coupler. 9. The device according to claim 1 , wherein the optical coupler is an edge optical coupler. 10. The device according to claim 1 , wherein the optical coupler is a vertical optical coupler.

Assignees

Inventors

Classifications

  • Glass (SiO2 based materials) · CPC title

  • high refractive index type, i.e. high-contrast waveguides · CPC title

  • by etching · CPC title

  • Three-dimensional structures · CPC title

  • by deposition of thin films · CPC title

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Frequently asked questions

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What does patent US11506840B2 cover?
An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.
Who is the assignee on this patent?
Elenion Tech Llc, Nokia Solutions & Networks Oy
What technology area does this patent fall under?
Primary CPC classification G02B6/134. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 22 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).