Back end of line process integrated optical device fabrication

Patent metadata

Field	Value
Publication number	US-9851506-B2
Application number	US-201514830046-A
Country	US
Kind code	B2
Filing date	Aug 19, 2015
Priority date	Jun 4, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.

First claim

What is claimed is:

1. A method of integrated optical device fabrication forming an optical device within a vertical span of a metal stack of an integrated semiconductor chip as part of a back end of line fabrication process, comprising:
providing a substrate with at least one semiconductor device thereon;
depositing a first layer comprising a dielectric over the semiconductor devices;
depositing a second layer comprising a first stop layer on the first layer;
depositing a third layer comprising a dielectric over the first stop layer;
etching a first portion of the third layer down to the first stop layer;
depositing metal in the first portion of the third layer for connection with external contacts;
connecting the metal to one of the at least one semiconductor device or other metal layer;
depositing a fourth layer comprising a second stop layer on the third layer; and
forming a second portion of the third layer into a first waveguide for coupling light to or from the at least one semiconductor device.

2. A method according to claim 1 , further comprising:
depositing a fifth layer comprising a dielectric over the second stop layer;
depositing a sixth layer comprising a third stop layer over the fifth layer;
depositing a seventh layer comprising a dielectric on the third stop layer;
etching a first portion of the seventh layer down to the third stop layer;
depositing metal in the first portion of the seventh layer for connection with external contacts;
connecting the second metal layer to one of the at least one semiconductor device; and
forming a second portion of the seventh layer into a second waveguide;
wherein forming the first and second waveguides comprises forming an edge coupler of a material having a first index of refraction greater than a second index of refraction of an oxide material in the third and seventh layers surrounding the input/output coupler.

3. A method according to claim 2 wherein forming the edge coupler comprises doping the oxide material to form a doped waveguide.

4. A method according to claim 3 wherein doping the oxide material to form the doped waveguide comprises doping utilizing at least one of ion implantation and diffusion and wherein the doping utilizes a material comprising at least one of B, F, Al, Ti, As, P, Er, Ni, Si, Cu, Zn, Ge, N, Zr, Nd, and Yb.

5. A method of integrated optical device fabrication forming an optical device within a vertical span of a metal stack of an integrated semiconductor chip as part of a back end of line fabrication process, comprising:
providing a substrate with at least one semiconductor device thereon;
depositing a first layer comprising a dielectric over the semiconductor devices;
depositing a second layer comprising a first stop layer on the first dielectric layer;
depositing a third layer comprising a dielectric over the first stop layer;
etching a first portion of the third layer down to the first stop layer;
depositing metal in the first portion of the third layer for connection with external contacts;
connecting the metal to one of the at least one semiconductor device or another metal layer;
depositing a fourth layer comprising a second stop layer on the third layer; and
forming a portion of one of the first stop layer and the second stop layer into a first waveguide for coupling light into or out of the at least one semiconductor device.

6. A method according to claim 5 , wherein forming the first stop layer comprises forming one of:
an etch stop layer; and
a chemical mechanical planarization stop layer.

7. A method according to claim 5 , wherein the first and second stop layers comprise at least one of silicon nitride, poly-silicon, and silicon oxynitride (SiON).

8. A method according to claim 5 , further comprising:
depositing a fifth layer comprising a dielectric over the second stop layer; and
depositing material within the fifth layer forming a third waveguide;
wherein at least one of the first and second waveguides form a vertical coupler with the third waveguide within the vertical span of the metal stack.

9. A method according to claim 8 wherein material deposition comprises deposition of at least one of silicon nitride, amorphous silicon, poly-silicon, silicon oxynitride, silicon-germanium (SiGe), SiO 2 , silicate glass, and germanium (Ge).

10. A method according to claim 9 wherein material deposition comprises deposition of a silicate glass comprising SiO 2 , and at least one of P 2 O 5 , B 2 O 3 , F, Al 2 O 3 , As 2 O 3 , GeO 2 , N 2 , TiO 2 , ZrO 2 , Nd 2 O 3 , Er 2 O 3 , and Yb 2 O 3 .

11. The method according to claim 5 , further comprising:
forming a portion of the other of the first stop layer and the second stop layer into a second waveguide for coupling light into or out of the at least one semiconductor device.

12. A method according to claim 11 , wherein the first and second waveguides comprise at least one of silicon nitride, poly-silicon, and silicon oxynitride (SiON), amorphous silicon, silicon-germanium (SiGe), SiO 2 , silicate glass, and germanium (Ge).

13. The method according to claim 11 , further comprising:
depositing a fifth layer comprising a dielectric over the second stop layer;
depositing a sixth layer comprising a third stop layer over the fifth layer; and
forming a third waveguide in a portion of the third stop layer;
wherein at least one of the first and second waveguides forms a vertical coupler with the third waveguide.

14. The method according to claim 13 , wherein the third waveguide comprises an arrayed waveguide grating (AWG).

15. The method according to claim 14 , wherein the AWG is more than 4 micrometers from the at least one semiconductor device.

16. The method according to claim 8 , wherein the third waveguide comprises a multimode interference coupler.

17. The method according to claim 5 , wherein at least one of the first and second waveguide comprises a tapered waveguide.

18. The method according to claim 5 , further comprising forming an edge coupler in another portion of the second stop layer.

Assignees

• Coriant Advanced Tech Llc
• Elenion Tech Llc

Inventors

• Shi Ruizhi
• Hochberg Michael J
• Novack Ari Jason
• Baehr-Jones Thomas Wetteland

Classifications

• G02B6/305

  and having an integrated mode-size expanding section, e.g. tapered waveguide · CPC title

• G02B6/1228

  Tapered waveguides, e.g. integrated spot-size transformers (for coupling with fibres G02B6/305) · CPC title

• G02B6/136

  by etching · CPC title

• G02B6/12002

  Three-dimensional structures · CPC title

• G02B6/132

  by deposition of thin films · CPC title