Memory cell with a ferroelectric capacitor integrated with a transtor gate

Patent metadata

Field	Value
Publication number	US-11502103-B2
Application number	US-201816114272-A
Country	US
Kind code	B2
Filing date	Aug 28, 2018
Priority date	Aug 28, 2018
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a “FE capacitor”). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.

First claim

The invention claimed is:

1. A memory cell, comprising:
a transistor comprising a fin and a gate; and
a ferroelectric (FE) capacitor comprising a first capacitor electrode, a second capacitor electrode, and a FE material between the first and second capacitor electrodes,
wherein:
a gate dielectric material of the gate wraps around an upper portion of the fin,
the first capacitor electrode includes a first conductor material, wherein the first conductor material at least partially wraps around the gate dielectric material,
the FE material at least partially wraps around the first conductor material, and
the second capacitor electrode includes a second conductor material over the FE material.

2. The memory cell according to claim 1 , wherein the second capacitor electrode is coupled to a word-line.

3. The memory cell according to claim 1 , wherein the transistor includes a first region of a pair of a source region and a drain region, the first region -coupled to a bit-line, and further includes a second region of the pair, the second region coupled to a select-line.

4. An integrated circuit (IC) device, comprising:
a fin comprising a semiconductor material; and
a gate stack over the semiconductor material of an upper portion of the fin, the gate stack comprising:
a gate dielectric material wrapping around the upper portion of the fin,
a first conductor material wrapping around the gate dielectric material,
a ferroelectric (FE) material wrapping around the first conductor material, and
a second conductor material at least partially over the FE material.

5. The IC device according to claim 4 , wherein:
the gate dielectric material is between the semiconductor material and the first conductor material,
the first conductor material is between the gate dielectric material and the FE material, and
the FE material is between the first conductor material and the second conductor material.

6. The IC device according to claim 4 , wherein the semiconductor material and the gate stack are parts of a transistor.

7. The IC device according to claim 6 , wherein the transistor includes a first region of a pair of a source region and a drain region, the first region coupled to a bit-line and a second region of the pair, the second region coupled to a select-line.

8. The IC device according to claim 6 , wherein the first conductor material, the FE material, and the second conductor material are parts of a FE capacitor integrated within the gate stack of the transistor.

9. The IC device according to claim 4 , further comprising a word-line, coupled to the second conductor material.

10. An integrated circuit (IC) package, comprising:
an IC die; and
a further component, coupled to the IC die,
wherein the IC die includes:
a fin comprising a semiconductor material,
a gate dielectric material wrapping around an upper portion of the fin,
a first conductor material wrapping around the gate dielectric material,
a ferroelectric (FE) material wrapping around the first conductor material, and
a second conductor material over at least a portion of the FE material.

11. The IC package according to claim 10 , wherein:
the IC die includes a transistor,
the semiconductor material is a channel material of the transistor,
the transistor includes a first region of a pair of a source region and a drain region, the first region coupled to a bit-line, and
the transistor further includes a second region of the pair, the second region coupled to a select-line.

12. The IC package according to claim 10 , wherein the second conductor material is coupled to a word-line.

13. The IC package according to claim 10 , wherein the FE material includes one or more of:
a material including hafnium, zirconium, and oxygen,
a material including silicon, hafnium, and oxygen,
a material including germanium, hafnium, and oxygen,
a material including aluminum, hafnium, and oxygen, and
a material including yttrium, hafnium, and oxygen.

14. A method of operating a memory cell comprising a transistor that includes a semiconductor material in a shape of a fin, and further includes a gate stack that includes a gate dielectric material, a first conductor material, a ferroelectric (FE) material, and a second conductor material, the method comprising:
driving a world-line (WL), coupled to the second conductor material, to cause the transistor to turn on; and
when the transistor is turned on, driving a bit-line (BL), coupled to a first region of a pair of a source region and a drain region of the transistor while a select-line (SL), coupled to a second region of the pair, is connected to a source supply voltage (Vss) or to zero Volts to program a logic state on the FE material,
wherein:
the gate dielectric material wraps around the upper portion of the fin,
the first conductor material wraps around the gate dielectric material,
the FE material wraps around the first conductor material, and
the second conductor material is at least partially over the FE material.

15. The method according to claim 14 , wherein the method includes:
applying a first set of voltages to the BL and the WL, while SL is connected to zero Volts, to cause a first logic state to be programmed on the FE material, and/or
applying a second set of voltages to the BL and the WL, while the SL connected to zero Volts, to
cause a second logic state to be programmed on the FE material.

16. The method according to claim 14 , further comprising:
after driving the BL to program the logic state on the FE material, switching the WL off.

17. The method according to claim 16 , further comprising:
turning the WL on and sensing the BL to determine the logic state programmed on the FE material.

18. The memory cell according to claim 1 , wherein a thickness of the first conductor material is between about 1 and 20 nanometers.

19. The IC device according to claim 4 , wherein the FE material is a thin-film FE material.

20. The IC device according to claim 4 , wherein the second conductor material encloses the FE material.

21. The IC package according to claim 10 , wherein a thickness of the first conductor material is between about 1 and 20 nanometers.

22. The IC package according to claim 10 , wherein the further component is one of a package substrate, a flexible substrate, or an interposer.

23. The method according to claim 14 , wherein the FE material is a thin-film FE material.

24. The method according to claim 14 , wherein the second conductor material encloses the FE material.

Assignees

• Intel Corp

Inventors

• Morris Daniel H
• Kim Seiyon
• Avci Uygar E
• Young Ian A

Classifications

• G11C11/2257

  Word-line or row circuits · CPC title

• G11C11/2253

  Address circuits or decoders · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title