Semiconductor device and transistor

Patent metadata

Field	Value
Publication number	US-9679893-B2
Application number	US-201514713000-A
Country	US
Kind code	B2
Filing date	May 15, 2015
Priority date	May 15, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

This disclosure provides a negative capacitance gate stack structure with a variable positive capacitor to implement a hysteresis free negative capacitance field effect transistors (NCFETs) with improved voltage gain. The gate stack structure provides an effective ferroelectric negative capacitor by using the combination of a ferroelectric negative capacitor and the variable positive capacitor with semiconductor material (such as polysilicon), resulting in the effective ferroelectric negative capacitor's being varied with an applied gate voltage. Our simulation results show that the NCFET with the variable positive capacitor can achieve not only a non-hysteretic I D -V G curve but also a better sub-threshold slope.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate; and
a gate structure over the substrate, the gate structure comprising:
a gate oxide;
a first metal layer over the gate oxide;
a ferroelectric material over the first metal layer;
a second metal layer over the ferroelectric material;
a semiconductor material over the second metal layer; and
a third metal layer over the semiconductor material,
wherein the second metal layer, the semiconductor material, and the third metal layer form a variable positive capacitor.

2. The semiconductor device of claim 1 , wherein the first metal layer, the ferroelectric material, and the second metal layer form a ferroelectric negative capacitor.

3. The semiconductor device of claim 2 , wherein the ferroelectric negative capacitor and the variable positive capacitor form an effective ferroelectric negative capacitor, wherein an absolute value of a capacitance of the effective ferroelectric negative capacitor is less than a capacitance of the gate oxide, and further wherein the absolute value of the capacitance of the effective ferroelectric negative capacitor is greater than a combination of the capacitance of the gate oxide and a depletion capacitance of the substrate.

4. The semiconductor device of claim 1 , wherein the variable positive capacitor varies with a gate voltage applied to the third metal layer.

5. The semiconductor device of claim 1 , wherein the semiconductor material includes polysilicon having a doping concentration of about 1e17/cm^3 to about 1e19/cm^3 and a thickness of about 10 nanometers to about 100 nanometers.

6. The semiconductor device of claim 1 , wherein the semiconductor material includes indium gallium zinc oxide having a doping concentration of about 1e16/cm^3 to about 1e19/cm^3 and a thickness of about 10 nanometers to about 100 nanometers.

7. The semiconductor device of claim 1 , further comprising:
a source over the substrate; and
a drain over the substrate and separated from the source,
wherein a gate voltage applied to the gate structure controls a channel between the source and the drain.

8. A semiconductor device, comprising:
a substrate; and
a gate structure on the substrate, the gate structure comprising:
a ferroelectric negative capacitor; and
a variable positive capacitor formed by a semiconductor material, wherein the ferroelectric capacitor and the variable positive capacitor form a hysteresis-free effective ferroelectric negative capacitor.

9. The semiconductor device of claim 8 , wherein the ferroelectric negative capacitor comprises a first metal layer, a ferroelectric material, and a second metal layer.

10. The semiconductor device of claim 8 , wherein the variable positive capacitor varies with a gate voltage applied to the gate structure.

11. The semiconductor device of claim 8 , wherein the semiconductor device is selected from the group consisting of planar devices, multi-gate devices, FinFETs, and gate-all-around FETs.

12. The semiconductor device of claim 8 , further comprising:
a source over the substrate; and
a drain over the substrate and separated from the source,
wherein a gate voltage applied to the gate structure controls a channel between the source and the drain.

13. A semiconductor device, comprising:
a substrate; and
a gate structure on the substrate, the gate structure comprising:
a ferroelectric negative capacitor; and
a variable positive capacitor formed by a semiconductor material,

wherein the variable positive capacitor is formed of a second metal layer, the semiconductor material, and a third metal layer.

14. A semiconductor device, comprising:
a substrate; and
a gate structure on the substrate, the gate structure comprising:
a ferroelectric negative capacitor; and
a variable positive capacitor formed by a semiconductor material,

wherein the ferroelectric negative capacitor and the variable positive capacitor form an effective ferroelectric negative capacitor, wherein an absolute value of a capacitance of the effective ferroelectric negative capacitor is less than a capacitance of a gate oxide of the gate structure, and further wherein the absolute value of the capacitance of the effective ferroelectric negative capacitor is greater than a combination of the capacitance of the gate oxide and a depletion capacitance of the substrate.

15. A semiconductor device, comprising:
a substrate; and
a gate structure on the substrate, the gate structure comprising:
a ferroelectric negative capacitor; and
a variable positive capacitor formed by a semiconductor material,

wherein the semiconductor material includes polysilicon having a doping concentration of about 1e17/cm^3 to about 1e19/cm^3 and a thickness of about 10 nanometers to about 100 nanometers.

16. A transistor, comprising:
a source;
a drain; and
a gate controlling conductivity between the source and the drain, the gate comprising:
a negative capacitor formed by a ferroelectric material; and
a variable positive capacitor formed by a semiconductor material, wherein the negative capacitor and the variable positive capacitor form a hysteresis-free effective ferroelectric capacitor.

17. The transistor of claim 16 , wherein the ferroelectric negative capacitor comprises a first metal layer, a ferroelectric material, and a second metal layer.

18. The transistor of claim 16 , wherein the variable positive capacitor varies with a gate voltage applied to the gate structure.

19. A transistor, comprising:
a source;
a drain; and
a gate controlling conductivity between the source and the drain, the gate comprising:
a negative capacitor formed by a ferroelectric material; and
a variable positive capacitor formed by a semiconductor material,

wherein the semiconductor material includes polysilicon having a doping concentration of about 1e17/cm^3 to about 1e19/cm^3 and a thickness of about 10 nanometers to about 100 nanometers.

20. A transistor, comprising:
a source;
a drain; and
a gate controlling conductivity between the source and the drain, the gate comprising:
a negative capacitor formed by a ferroelectric material; and
a variable positive capacitor formed by a semiconductor material,

wherein the negative capacitor and the variable positive capacitor form an effective ferroelectric capacitor, wherein an absolute value of a capacitance of the effective ferroelectric negative capacitor is less than a capacitance of a gate oxide of the gate, and further wherein the absolute value of the capacitance of the effective ferroelectric capacitor is greater than a combination of the capacitance of the gate oxide and a depletion capacitance of the substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Yan Jhih-Yang
• Liu Chee-Wee
• Lai Der-Chuan

Classifications

• H01L27/0711 Primary

  Electricity · mapped topic

• H01L28/55

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic

• H10D84/813 Primary

  Combinations of field-effect devices and capacitor only · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title