Selective metal deposition by patterning direct electroless metal plating

Patent metadata

Field	Value
Publication number	US-11501967-B2
Application number	US-201916269357-A
Country	US
Kind code	B2
Filing date	Feb 6, 2019
Priority date	Feb 6, 2019
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

First claim

What is claimed is:

1. A package substrate, comprising:
a self-assembled monolayer (SAM) layer over a first dielectric layer includes a top surface and a bottom surface opposite to the top surface and a second dielectric layer over a top surface of the SAM layer, wherein the SAM layer includes a plurality of first end groups and a plurality of second end groups, and wherein the plurality of second end groups includes a plurality of hydrophobic fluorinated moieties;
a conductive pad on the first dielectric layer, wherein the conductive pad has a bottom surface, a top surface, and a sidewall, and wherein the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad;
wherein a top surface of the second dielectric layer is coplanar with the top surface of the conductive pad and the bottom surface of the SAM layer is coplanar with the bottom surface of the conductive pad and the top surface of the first dielectric layer;
wherein the plurality of first end groups attaches to the bottom surface of the SAM layer and the top surface of the first dielectric layer and the plurality of second end groups attaches to the top surface of the SAM layer, wherein the bottom surface of the second dielectric layer is above the plurality of second end groups of the SAM layer.

2. The package substrate of claim 1 , wherein the top surface of the conductive pad is a flat surface, wherein the flat surface of the conductive pad is parallel to the top surface of the first dielectric layer, wherein the conductive pad includes a copper material, and wherein the sidewall of the conductive pad is a tapered sidewall or a vertical sidewall.

3. The package substrate of claim 2 , wherein the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material, and wherein the surface roughness of the top surface of the conductive pad includes a first roughness, a second roughness, or a third roughness.

4. The package substrate of claim 3 , wherein the first roughness of the top surface of the conductive pad is approximately less than 2 nm, wherein the second roughness of the top surface of the conductive pad is approximately 1-18 nm, or wherein the third roughness of the top surface of the conductive pad is approximately 1-50 nm.

5. The package substrate of claim 1 , wherein the second dielectric layer has a top surface and a bottom surface that is opposite to the top surface.

6. The package substrate of claim 5 , wherein the plurality of first end groups includes one or more molecular compounds, wherein the one or more molecular compounds includes a silicon molecular compound, a nitrogen molecular compound, an oxygen compound, an unsaturated aliphatic molecular compound, or an aromatic molecular compound, wherein the plurality of first end groups attaches to the bottom surface of the SAM layer and the top surface of the first dielectric, wherein the plurality of second end groups attaches to the top surface of the SAM layer, wherein the bottom surface of the second dielectric is above the plurality of second end groups of the SAM layer, and wherein the top surface of the second dielectric is substantially coplanar to the surface roughness of the top surface of the conductive pad.

7. The package substrate of claim 1 , wherein the SAM layer has a thickness that is approximately 0.1 nm to 20 nm.

8. A semiconductor packaged system, comprising:
a substrate on a packaged substrate; and
a die on the substrate, wherein the packaged substrate or the substrate include:
a self-assembled monolayer (SAM) layer over a first dielectric layer includes a top surface and a bottom surface opposite to the top surface and a second dielectric layer over a top surface of the SAM layer, wherein the SAM layer includes a plurality of first end groups and a plurality of second end groups, and wherein the plurality of second end groups includes a plurality of hydrophobic fluorinated moieties;
a conductive pad on the first dielectric, wherein the conductive pad has a bottom surface, a top surface, and a sidewall, and wherein the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad;
wherein a top surface of the second dielectric layer is coplanar with the top surface of the conductive pad and the bottom surface of the SAM layer is coplanar with the bottom surface of the conductive pad and the top surface of the first dielectric layer; and
wherein the plurality of first end groups attaches to the bottom surface of the SAM layer and the top surface of the first dielectric layer and the plurality of second end groups attaches to the top surface of the SAM layer, wherein the bottom surface of the second dielectric layer is above the plurality of second end groups of the SAM layer.

9. The semiconductor packaged system of claim 8 , wherein the top surface of the conductive pad is a flat surface, wherein the flat surface of the conductive pad is parallel to the top surface of the first dielectric layer, wherein the conductive pad includes a copper material, wherein the sidewall of the conductive pad is a tapered sidewall or a vertical sidewall.

10. The semiconductor packaged system of claim 9 , wherein the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material, and wherein the surface roughness of the top surface of the conductive pad includes a first roughness, a second roughness, or a third roughness.

11. The semiconductor packaged system of claim 10 , wherein the first roughness of the top surface of the conductive pad is approximately less than 2 nm, wherein the second roughness of the top surface of the conductive pad is approximately 1-18 nm, or wherein the third roughness of the top surface of the conductive pad is approximately 1-50 nm.

12. The semiconductor packaged system of claim 8 , wherein the plurality of first end groups includes one or more molecular compounds, wherein the one or more molecular compounds includes a silicon molecular compound, a nitrogen molecular compound, an oxygen molecular compound, an unsaturated aliphatic molecular compound, or an aromatic molecular compound, wherein the top surface of the second dielectric layer is coplanar to the surface roughness of the top surface of the conductive pad, and wherein the SAM layer has a thickness that is approximately 0.1 nm to 20 nm.

Assignees

• Intel Corp

Inventors

• Nad Suddhasattwa
• Dittler Roy
• Grujicic Darko
• Wall Marcel
• Manepalli Rahul

Classifications

• H10P14/432

  using selective deposition · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W20/044

  for electroless plating · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title