Circuit screening system and circuit screening method

Patent metadata

Field	Value
Publication number	US-11500016-B2
Application number	US-202017114330-A
Country	US
Kind code	B2
Filing date	Dec 7, 2020
Priority date	Dec 7, 2020
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.

First claim

What is claimed is:

1. A circuit screening system, comprising:
a target circuit under test, configured to receive a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal;
a power circuit, coupled to the target circuit under test, configured to provide a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period; and
a clock generating circuit, configured to provide a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period to trigger the target circuit under test receive to receive the first testing signal in the first period and the second testing signal in the second period;
wherein the clock signal has a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile have a phase difference.

2. The circuit screening system of claim 1 , wherein the phase difference between the first profile and the second profile are 90 degrees.

3. The circuit screening system of claim 1 , wherein the clock signal provided in the first period includes a plurality of integrated pulses, and the clock signal provided in the second period includes a plurality of half pulses.

4. The circuit screening system of claim 3 , wherein a profile of the clock signal provided in the second period excludes a falling edge.

5. The circuit screening system of claim 3 , wherein a profile of the clock signal provided in the second period excludes a rising edge.

6. The circuit screening system of claim 1 , wherein the power circuit is further configured to pulls up the voltage level of the supply voltage to the second voltage level after the second period.

7. A circuit screening system, comprising:
a signal generating circuit, arranged to generate a testing signal;
a target circuit under test, including a plurality of flip-flops in cascade connection and a cluster of logic circuits coupled to the flip-flops, wherein the plurality of flip-flops transfer the testing signal to the cluster of logic circuits;
a power circuit, configured to provide a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage is located in an input range in a first period, in a stress range higher than the input range in a second period after the first period, and located in the input range in a third period after the second period; and
a clock generating circuit, arranged to provide a clock signal having a first profile to the target circuit under test in the first period, and provide the clock signal having a second profile to the target circuit under test in the second period;
wherein the first profile and the second profile are different;
wherein the clock signal has a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile have a phase difference.

8. The circuit screening system of claim 7 , wherein the clock signal having the first profile includes a plurality of integrated pulses to trigger the plurality of flip-flops to receive the testing signal as a first testing signal in the first period, and the clock signal having the second profile to trigger the plurality of flip-flops to receive the testing signal as a second testing signal in the second period.

9. The circuit screening system of claim 8 , wherein the clock signal having the second profile triggers the plurality of flip-flops to shift the first testing signal at least one bit to obtain the second testing signal.

10. The circuit screening system of claim 8 , wherein the second testing signal and the second testing signal are complementary.

11. The circuit screening system of claim 8 , wherein the testing signal provided by the signal generating circuit in the first period is different from the testing signal provided by the signal generating circuit in the second period.

12. The circuit screening system of claim 7 , wherein the voltage level of the supply voltage is further located in the stress range in a fourth period after the third period, and located in an off range lower than the input range in a fifth period after the fourth period.

13. The circuit screening system of claim 12 , wherein the voltage level of the supply voltage is further located in the stress range in a sixth period after the fifth period.

14. The circuit screening system of claim 12 , wherein the voltage level located in the off range smaller than a threshold voltage of a transistor of the target circuit under test.

15. A circuit screening method, comprising:
operating in a first input stage, in which a first testing signal is inputted into a target circuit under test, a supply voltage, whose voltage level locates in an input range, is provided to the target circuit under test, and a clock signal having a first profile is provided to the target circuit under test;
operating in a first stress stage after the first input stage, in which the voltage level of the supply voltage locates in a stress range higher than the input range;
operating in a second input stage after the first stress stage, in which a second testing signal different from the first testing signal is inputted into the test target circuit under test, and the supply voltage, whose voltage level relocates in the input range from the stress range, is provided to the test target circuit under test, and a clock signal having a second profile different from the first profile is provided to the target circuit under test;
wherein the first profile and the second profile have a phase difference.

16. The circuit screening method of claim 15 , operating in the second input stage after the first stress stage further comprising:
generating the clock signal having the second profile by inversing the clock signal having the first profile; and
inputting the second signal having the second profile to the target circuit under test.

17. The circuit screening method of claim 15 , operating in the second input stage after the first stress stage further comprising:
generating the clock signal having the second profile by generating a logic high value, pulling down the logic high value to a logic low value, and stopping generating the clock signal; and
inputting the second signal having the second profile to the target circuit under test.

18. The circuit screening method of claim 15 , operating in the second input stage after the first stress stage further comprising:
generating the clock signal having the second profile by generating a logic low value, rising the logic low value to a logic high value, stopping generating the clock signal; and
inputting the second signal having the second profile to the target circuit under test.

19. The circuit screening method of claim 15 , further comprising:
operating in an off stage after the second input stage, in which the supply voltage, whose voltage level locates in an off range lower than the input range, is provided to the test target circuit under test.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chi-Che
• Hung Tsung-Yang
• Guo Jia-Ming
• Fang Edna
• Wang Ming-Yih

Classifications

• G01R31/31712

  Input or output aspects · CPC title

• G01R31/2879

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title

• G01R31/31725 Primary

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/3004

  Current or voltage test · CPC title

• G01R31/3183

  Generation of test inputs, e.g. test vectors, patterns or sequences · CPC title