Trace controller for processor, periphery, address, control, and data lines

Patent metadata

Field	Value
Publication number	US-9218263-B2
Application number	US-201514802685-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Feb 8, 1989
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

First claim

What is claimed is:

1. A system comprising:
address lines, control lines, and data lines;
processor circuitry coupled to the address lines, the control lines, and the data lines;
peripheral circuitry coupled to the address lines, the control lines, and the data lines; and
trace domain circuitry coupled to the address lines, the control lines, and the data lines, the trace domain circuitry including:
trace controller circuitry having inputs coupled to the address lines, the…

Assignees

• Texas Instruments Inc

Inventors

• Whetsel Lee D

Classifications

• G01R31/318572 Primary

  Physics · mapped topic

• G01R31/31723 Primary

  Physics · mapped topic

• G06F11/27 Primary

  Physics · mapped topic

• G06F11/267

  Physics · mapped topic

• G01R31/31722

  Physics · mapped topic