Pipeline including separate hardware data paths for different instruction types

Patent metadata

Field	Value
Publication number	US-11494192-B2
Application number	US-202016860842-A
Country	US
Kind code	B2
Filing date	Apr 28, 2020
Priority date	Oct 21, 2016
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

First claim

What is claimed is:

1. An apparatus comprising:
a pipeline configured to support a first set of instructions and a second set of instructions, the pipeline including at least a first hardware data path and a second hardware data path;
a first processing element implemented in a first stage of the pipeline and configured to execute an instruction, wherein:
a first portion of the first hardware data path provides information associated with the instruction to the first processing element in response to the instruction being in the first set of instructions;
a first portion of the second hardware data path provides information associated with the instruction to the first processing element in response to the instruction being in the second set of instructions; and
the second hardware data path includes an output register configured to receive data from the first processing element; and

a control unit to gate at least one of power or a clock signal provided to the first portion of the first hardware data path in response to the instruction being in the second set of instructions.

2. The apparatus of claim 1 , wherein the second set of instructions is a subset of the first set of instructions.

3. The apparatus of claim 1 , wherein:
the second set of instructions includes instructions executed by the pipeline at or above a threshold frequency; and
the first set of instructions includes instructions executed by the pipeline below the threshold frequency.

4. The apparatus of claim 1 , wherein the first set of instructions includes at least ten times as many instructions as the second set of instructions.

5. The apparatus of claim 1 , wherein the control unit determines that the instruction is in the second set of instructions based on an opcode of the instruction received by the first stage of the pipeline.

6. The apparatus of claim 1 , further comprising:
at least one second portion of the first hardware data path configured to receive outputs from the first portion of the first hardware data path and the first portion of the second hardware data path and to selectively provide an output from the first portion of the first hardware data path or the first portion of the second hardware data path to the first processing element based on signaling from the control unit.

7. The apparatus of claim 6 , wherein the at least one second portion of the first hardware data path provides the output from the first portion of the second hardware data path to the first processing element in response to the control unit gating the at least one of the power or the clock signal provided to the first portion of the first hardware data path.

8. The apparatus of claim 1 , further comprising:
first input registers to store information associated with the instruction and provide the information to inputs of the first portion of the first hardware data path; and
second input registers to store the information associated with the instruction and provide the information to the inputs of the first portion of the second hardware data path.

9. The apparatus of claim 8 , further comprising:
a second processing element implemented in a second stage of the first hardware data path and configured to execute the instruction;
first output registers to receive information generated by the first processing element;
a second portion of the first hardware data path to receive information stored in the first output registers and to provide an output of the first output registers to the second processing element;
second output registers to receive the information generated by the first processing element;
a second portion of the second hardware data path to receive information stored in the second output registers and to provide output to the second processing element; and
wherein the control unit is configured to gate at least one of power or a clock signal provided to the second portion of the first hardware data path in response to the instruction being in the second set of instructions.

10. A method comprising:
receiving an instruction at a first stage of a pipeline of a processing device, the pipeline including at least a first hardware data path and a second hardware data path;
providing information associated with the instruction from a first portion of the first hardware data path of the processing device to a first processing element implemented in the first stage of the first hardware data path in response to the instruction being in a first set of instructions;
providing information associated with the instruction from a first portion of the second hardware data path of the processing device to the first processing element in response to the instruction being in a second set of instructions, wherein the second hardware data path includes an output register configured to receive data from the first processing element; and
gating at least one of power or a clock signal provided to the first portion of the first hardware data path in response to the instruction being in the second set of instructions.

11. The method of claim 10 , further comprising:
determining that the received instruction is in the second set of instructions based on an opcode of the received instruction received by the first stage of the pipeline.

12. The method of claim 10 , further comprising:
selectively providing output from the first portion of the first hardware data path or the first portion of the second hardware data path to the first processing element based on signaling from a control unit.

13. The method of claim 12 , wherein providing the output comprises providing the output from the first portion of the second hardware data path to the first processing element in response to the control unit gating the at least one of the power or the clock signal provided to the first portion of the first hardware data path.

14. The method of claim 13 , further comprising:
receiving the instruction at a second stage of the pipeline that includes a second processing element configured to execute the instruction;
receiving information generated by the first processing element;
providing information associated with the instruction from a second portion of the first hardware data path of the processing device to the second processing element in response to the instruction being in the first set of instructions;
providing the information associated with the instruction from a second portion of the second hardware data path of the processing device to the second processing element in response to the instruction being in the second set of instructions; and
gating at least one of power or a clock signal provided to the second portion of the first hardware data path in response to the instruction being in the second set of instructions.

15. An apparatus comprising:
a first hardware data path including:
a first processing element implemented in a first stage of a pipeline and configured to execute an instruction;
a first portion to provide information associated with the instruction to the first processing element in response to the instruction being in a first set of instructions;

a second hardware data path configured to execute half-precision floating-point instructions and to receive information generated by the first processing element in the first hardware data path and including:
a first portion to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions; and
an output register configured to receive data from the first processing element; and

a con

Assignees

• Advanced Micro Devices Inc
• Advanced Micro Devices Shanghai Co Ltd

Inventors

• Chen Jiasheng
• Zou Yunxiao
• He Bin
• Socarras Angel E
• Wang Qingcheng
• Yuan Wei
• Mantor Michael

Classifications

• G06F9/3869 Primary

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title

• G06F2015/768

  Gate array · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title