Pipeline including separate hardware data paths for different instruction types

Patent metadata

Field	Value
Publication number	US-10656951-B2
Application number	US-201715789318-A
Country	US
Kind code	B2
Filing date	Oct 20, 2017
Priority date	Oct 21, 2016
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

First claim

What is claimed is:

1. An apparatus comprising:
a first processing element implemented in a first stage of a pipeline and configured to execute an instruction;
a first array of multiplexers to provide information associated with the instruction to the first processing element in response to the instruction being in a first set of instructions;
a second array of multiplexers to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions; and
a control unit to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

2. The apparatus of claim 1 , wherein the second set of instructions is a subset of the first set of instructions.

3. The apparatus of claim 1 , wherein:
the second set of instructions includes instructions executed by the pipeline at or above a threshold frequency; and
the first set of instructions includes instructions executed by the pipeline below the threshold frequency.

4. The apparatus of claim 1 , wherein the first set of instructions includes at least ten times as many instructions as the second set of instructions.

5. The apparatus of claim 1 , wherein the control unit determines that the received instruction is in the second set based on an opcode of the first instruction received by the first stage of the pipeline.

6. The apparatus of claim 1 , further comprising:
at least one third multiplexer to receive output from the first array of multiplexers and the second array of multiplexers and to selectively provide an output from the first array of multiplexers or the second array of multiplexers to the first processing element based on signaling from the control unit.

7. The apparatus of claim 6 , wherein the at least one third multiplexer provides the output from the second array of multiplexers to the first processing element in response to the control unit gating the at least one of the power or the clock signal provided to the first array of multiplexers.

8. The apparatus of claim 1 , further comprising:
first input registers to store information associated with the instruction and provide the information to inputs of the first array of multiplexers; and
second input registers to store the information associated with the instruction and provide the information to the inputs of the second array of multiplexers.

9. The apparatus of claim 8 , further comprising:
a second processing element implemented in a second stage of the pipeline and configured to execute the instruction;
first output registers to receive information generated by the first processing element;
a third array of multiplexers to receive information stored in the first output registers and to provide output to the second processing element;
second output registers to receive the information generated by the first processing element;
a fourth array of multiplexers to receive information stored in the second output registers and to provide output to the second processing element; and
wherein the control unit is configured to gate at least one of power or a clock signal provided to the third array of multiplexers in response to the instruction being in the second set.

10. A method comprising:
receiving an instruction at a first stage of a pipeline of a processing device;
providing information associated with the instruction from a first array of multiplexers of the processing device to a first processing element implemented in the first stage in response to the instruction being in a first set of instructions;
providing information associated with the instruction from a second array of multiplexers of the processing device to the first processing element in response to the instruction being in a second set of instructions; and
gating at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

11. The method of claim 10 , further comprising:
determining that the received instruction is in the second set based on an opcode of the received instruction received by the first stage of the pipeline.

12. The method of claim 10 , further comprising:
selectively providing output from the first array of multiplexers or the second array of multiplexers to the first processing element based on signaling from a control unit.

13. The method of claim 12 , wherein providing the output comprises providing the output from the second array of multiplexers to the first processing element in response to the control unit gating the at least one of the power or the clock signal provided to the first array of multiplexers.

14. The method of claim 13 , further comprising:
receiving the instruction at a second stage of the pipeline that includes a second processing element configured to execute the instruction;
receiving information generated by the first processing element;
providing information associated with the instruction from a third array of multiplexers of the processing device to the second processing element in response to the instruction being in the first set;
providing the information associated with the instruction from a fourth array of multiplexers of the processing device to the second processing element in response to the instruction being in the second set; and
gating at least one of power or a clock signal provided to the third array of multiplexers in response to the instruction being in the second set.

15. An apparatus comprising:
a first hardware data path including:
a first processing element implemented in a first stage of a pipeline and configured to execute an instruction; and
a first array of multiplexers to provide information associated with the instruction to the first processing element in response to the instruction being in a first set of instructions;

a second hardware data path configured to execute half-precision floating-point instructions and to receive information generated by the first processing element in the first hardware data path;
a second array of multiplexers to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions; and
a control unit to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

16. The apparatus of claim 15 , wherein the second set of instructions includes instructions that are executed by the pipeline more frequently than a threshold frequency, and wherein the first set of instructions includes instructions that are executed by the pipeline less frequently than the threshold frequency.

17. The apparatus of claim 15 , wherein the control unit determines that the received instruction is in the second set based on an opcode of the instruction received by the first stage of the pipeline.

18. The apparatus of claim 15 , wherein the second hardware data path comprises a third array of multiplexers implemented in a second stage of the pipeline to provide information to a second processing element implemented on the first hardware data path in the second stage of the pipeline in response to the instruction being in the second set.

19. The apparatus of claim 18 , wherein the control unit is configured to gate at least one of power or a clock signal provided to a fourth array of multiplexers implemented on the first hardware data path in th

Assignees

• Advanced Micro Devices Inc
• Advanced Micro Devices Shanghai Co Ltd

Inventors

• Chen Jiasheng
• Zou Yunxiao
• He Bin
• Socarras Angel E
• Wang Qingcheng
• Yuan Wei
• Mantor Michael

Classifications

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3869 Primary

  Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F2015/768

  Gate array · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title