Semiconductor chip package and method of assembly

Patent metadata

Field	Value
Publication number	US-11488903-B2
Application number	US-202117160917-A
Country	US
Kind code	B2
Filing date	Jan 28, 2021
Priority date	Jan 28, 2020
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A semiconductor device substrate assembly may include a first substrate, comprising: a first insulator plate; and a first patterned metal layer, disposed on the first insulator plate, wherein the first insulator plate comprises a first material and a first thickness. The assembly may include a second substrate, comprising: a second insulator plate; and a second patterned metal layer, disposed on the second insulator plate, wherein the second insulator plate comprises the first material and the first thickness. The assembly may also include a third substrate, disposed between the first substrate and the second substrate, comprising: a third insulator plate; and a third patterned metal layer, disposed on the third insulator plate, wherein the third insulator plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness differs from the first material and the first thickness, respectively.

First claim

What is claimed is:

1. A semiconductor device substrate assembly, comprising:
a first substrate, comprising:
a first insulator plate; and
a first patterned metal layer, disposed on the first insulator plate, wherein the first insulator plate comprises a first material and a first thickness;

a second substrate, comprising:
a second insulator plate; and
a second patterned metal layer, disposed on the second insulator plate, wherein the second insulator plate comprises the first material and the first thickness; and

a third substrate, disposed between the first substrate and the second substrate, comprising:
a third insulator plate; and
a third patterned metal layer, disposed on the third insulator plate, wherein the third insulator plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness differs from the first material and the first thickness, respectively.

2. The semiconductor device substrate assembly of claim 1 , the first insulator plate and the second insulator plate comprising a first insulator material having a first thermal conductivity, and the third insulator plate comprising a second insulator material having a second thermal conductivity, less than the first thermal conductivity, while having mechanical properties that are more robust against a mechanical stress of a busbar attachment process.

3. The semiconductor device substrate assembly of claim 2 , the first insulator material comprising silicon nitride or aluminum nitride, and the second insulator material comprising aluminum nitride or aluminum oxide.

4. The semiconductor device substrate assembly of claim 1 , wherein the second thickness is greater than the first thickness.

5. The semiconductor device substrate assembly of claim 1 , wherein the first patterned metal layer and the second patterned metal layer comprise a first layer thickness, and wherein the third patterned metal layer comprises a second layer thickness, different from the first layer thickness.

6. The semiconductor device substrate assembly of claim 1 , the first patterned metal layer and the second patterned metal layer being shaped to accommodate a plurality of semiconductor die, disposed thereupon, and .third patterned metal layer comprising a plurality of patterned structures to accommodate a bus bar assembly, disposed thereupon.

7. The semiconductor device substrate assembly of claim 1 , further comprising a baseplate, wherein the first substrate, second substrate and third substrate are disposed on the baseplate.

8. The semiconductor device substrate assembly of claim 1 , further comprising a fourth substrate, disposed adjacent the first substrate, on a first side of the third substrate; and
a fifth substrate, disposed adjacent the second substrate, on a second side of the third substrate.

9. A semiconductor device package, comprising:
a first substrate, comprising:
a first insulator plate; and
a first patterned metal layer, disposed on the first insulator plate; and
a first set of semiconductor die, disposed on the first patterned metal layer;

a second substrate, comprising:
a second insulator plate;
a second patterned metal layer, disposed on the second insulator plate; and
a second set of semiconductor die, disposed on the second patterned metal layer;

a third substrate, disposed between the first substrate and the second substrate, comprising:
a third insulator plate; and
a third patterned metal layer, disposed on the third insulator plate; and

a set of busbars, connected to the third patterned metal layer.

10. The semiconductor device package of claim 9 , the first insulator plate and the second insulator plate comprising a first insulator material having a first thickness, and the third insulator plate comprising a second insulator material having a second thickness, greater than the first thickness.

11. The semiconductor device package of claim 10 , the first insulator material comprising silicon nitride, aluminum nitride or aluminum oxide, and the second insulator material comprising aluminum nitride or aluminum oxide.

12. The semiconductor device package of claim 9 , further comprising:
a first set of semiconductor die, disposed on the first patterned metal layer;
a second set of semiconductor die, disposed on the second patterned metal layer;
a set of busbars, connected to the third patterned metal layer; and
a first set of connectors, electrically connecting the third patterned metal layer to the first patterned metal layer and a second set of connectors electrically connecting the third patterned metal layer to the second patterned metal layer.

13. The semiconductor device package of claim 12 , wherein the first set of semiconductor die and the second set of semiconductor die comprise a set of power semiconductor devices.

14. The semiconductor device package of claim 9 , further comprising a baseplate, wherein the first substrate, second substrate and third substrate are disposed on the baseplate.

15. The semiconductor device package of claim 10 , the first insulator material comprising silicon nitride or aluminum nitride, and the second insulator material comprising aluminum nitride or aluminum oxide.

16. The semiconductor device package of claim 9 , the first insulator plate and the second insulator plate comprising a first insulator material having a first thermal conductivity, and the third insulator plate comprising a second insulator material having a second thermal conductivity, less than the first thermal conductivity.

Assignees

• Littelfuse Inc

Inventors

• Steinhoff Stefan

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/023

  Connecting or disconnecting interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W72/075

  of bond wires · CPC title