Memory devices including void spaces between transistor features, and related semiconductor devices and electronic systems

Patent metadata

Field	Value
Publication number	US-11476259-B2
Application number	US-202117301793-A
Country	US
Kind code	B2
Filing date	Apr 14, 2021
Priority date	Oct 9, 2018
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.

First claim

What is claimed is:

1. A memory device, comprising:
a digit line; and
a transistor in electrical communication with the digit line and comprising:
a drain structure vertically overlying the digit line;
a channel structure vertically overlying the drain structure and comprising an oxide semiconductor material;
a source structure vertically overlying the channel structure;
a gate electrode vertically overlying the digit line and horizontally neighboring the channel structure, the gate electrode comprising:
an upper surface above an upper vertical boundary of the channel structure; and
a lower surface below a lower vertical boundary of the channel structure;

a gate dielectric material horizontally extending from and between the channel structure and the gate electrode;
a first void space horizontally interposed between the drain structure and the gate electrode and vertically interposed between the gate dielectric material and the digit line; and
a second void space horizontally interposed between the source structure and the gate electrode and vertically interposed between the gate dielectric material and an additional dielectric material covering surfaces of the source structure, the gate electrode, and the digit line.

2. The memory device of claim 1 , wherein an upper vertical boundary of the first void space underlies the lower vertical boundary of the channel structure.

3. The memory device of claim 2 , wherein a lower vertical boundary of the second void space overlies the upper vertical boundary of the channel structure.

4. The memory device of claim 1 , wherein a lower vertical boundary of the first void space is vertically offset from a lower vertical boundary of the drain structure.

5. The memory device of claim 4 , wherein the lower vertical boundary of the first void space is substantially coplanar with the lower surface of the gate electrode.

6. The memory device of claim 4 , wherein an additional dielectric material is vertically interposed between:
the lower surface of the gate electrode and the digit line; and
the lower vertical boundary of the first void space and the digit line.

7. The memory device of claim 1 , wherein an upper vertical boundary of the second void space is vertically offset from an upper vertical boundary of the source structure.

8. The memory device of claim 7 , wherein the upper vertical boundary of the second void space is substantially coplanar with the upper surface of the gate electrode.

9. The memory device of claim 1 , wherein the oxide semiconductor material of the channel structure has a larger band gap than polycrystalline silicon.

10. The memory device of claim 9 , wherein the drain structure and the source structure each comprise one or more of tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, and gold.

11. A semiconductor device, comprising:
a transistor overlying an electrically conductive line structure, the transistor comprising:
a pillar structure comprising:
a drain region comprising a first electrically conductive material;
a source region comprising a second electrically conductive material; and
a channel region comprising a semiconductor material interposed between the drain region and the source region;

a gate electrode neighboring the pillar structure, the gate electrode comprising:
an upper boundary overlying an upper boundary of the channel region of the pillar structure; and
a lower boundary underlying a lower boundary of the channel region of the pillar structure; and

gate dielectric material interposed between the pillar structure and the gate electrode;

additional dielectric material on the transistor and the electrically conductive line structure;
a first electrically insulative space overlying the gate dielectric material and interposed between the pillar structure and the gate electrode; and
a second electrically insulative space underlying the gate dielectric material and interposed between the pillar structure and the gate electrode.

12. The semiconductor device of claim 11 , wherein:
a horizontal width of the channel region of the pillar structure is within a range of from about 500 Å to about 2000 Å; and
a vertical height of the channel region of the pillar structure is within a range of from about 300 Å to about 2000 Å.

13. The semiconductor device of claim 12 , wherein:
a horizontal width of the gate electrode is within a range of from about 30 Å to about 150 Å; and
a vertical height of the gate electrode is greater than the vertical height of the channel region of the pillar structure.

14. The semiconductor device of claim 13 , wherein:
a horizontal width of the gate dielectric material is within a range of from about 10 Å to about 100 Å; and
a vertical height of the gate dielectric material is less than the vertical height of the gate electrode.

15. The semiconductor device of claim 14 , wherein a ratio of the vertical height of the gate dielectric material to the vertical height of the gate electrode is within a range of from about 1:2 to about 1:10.

16. The semiconductor device of claim 14 , wherein:
a horizontal width of each of the first electrically insulative space and the second electrically insulative space is substantially equal to the horizontal width of the gate dielectric material; and
a vertical height of each of the first electrically insulative space and the second electrically insulative space is within a range of from about 100 Å to about 450 Å.

17. The semiconductor device of claim 11 , wherein:
the first electrically insulative space vertically extends from an upper surface of the gate dielectric material to a portion of the additional dielectric material; and
the second electrically insulative space vertically extends from a lower surface of the gate dielectric material to an additional portion of the additional dielectric material.

18. An electronic system, comprising:
an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device, the memory device comprising:
a vertical transistor vertically overlying a digit line structure and comprising:
a drain structure on the digit line structure and comprising conductive material;
a channel structure on the drain structure and comprising semiconductor material;
a source structure on the channel structure and comprising additional conductive material;
a gate electrode horizontally neighboring the channel structure and comprising:
an upper surface vertically offset from an upper boundary of the channel structure; and
a lower surface vertically offset from a lower boundary of the channel structure; and

gate dielectric material horizontally extending from the channel structure to the gate electrode;

additional dielectric material covering the vertical transistor and the digit line structure;
a void space vertically below the gate dielectric material and horizontally extending from the drain structure to the gate electrode; and
an additional void space vertically above the gate dielectric material and horizontally extending from the source structure to the gate electrode.

19. The electronic system of claim 18 , wherein:
a vertical dimension of the gate electrode is greater than a vertical dimension of the channel structure; and
a vertical dimension of the gate dielectric material is greater than the vertical dimension of the channel structure and less tha

Assignees

• Karda Kamal M
• Gandhi Ramanathan
• Li Hong
• Liu Haitao
• Ramaswamy Durai Vishak Nirmal
• Tang Sanh D
• Sills Scott E
• Micron Technology Inc

Inventors

• Karda Kamal M
• Gandhi Ramanathan
• Li Hong
• Liu Haitao
• Ramaswamy Durai Vishak Nirmal
• Tang Sanh D
• Sills Scott E

Classifications

• H01L27/11273 Primary

  Electricity · mapped topic

• H01L29/1037

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/42364

  Electricity · mapped topic