Inverter

Patent metadata

Field	Value
Publication number	US-11476179-B2
Application number	US-201615334090-A
Country	US
Kind code	B2
Filing date	Oct 25, 2016
Priority date	Oct 25, 2016
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

First claim

What is claimed is:

1. A transistor package comprising:
a substrate;
a transistor in thermal contact with the substrate;
the substrate sintered to a heat sink through a sintered layer;
an encapsulant that at least partially encapsulates the transistor;
a Kelvin connection, the Kelvin connection having a first connector directly coupled at a first end to a transistor gate of the transistor and a second connector directly coupled at a first end to a differing terminal of the transistor, wherein the encapsulant further encapsulates a portion of each of the first connector and the second connector, including the first end of the first connector and the first end of the second connector; and
an external busbar connector, the connector having a “U”-bend shape and a busbar connector interconnecting the transistor to either a positive busbar or a negative busbar for providing current to the transistor.

2. The transistor package of claim 1 , wherein the heat sink comprises fins and contact pads.

3. The transistor package of claim 1 , further comprising a diode structure that is in series with the transistor.

4. The transistor package of claim 3 , wherein the transistor is an insulated-gate bipolar transistor.

5. The transistor package of claim 3 , wherein the transistor is a metal-oxide-semiconductor-field-effect transistor.

6. The transistor package of claim 1 , wherein the transistor package further comprises a cladding layer.

7. The transistor package of claim 1 , wherein the transistor comprises a gallium nitride or a silicon carbide wideband semiconductor.

8. The transistor package of claim 6 , wherein the cladding layer is at least one of an n-type or p-type cladding layer.

9. The transistor package of claim 6 , wherein the cladding layer is a copper cladding layer.

10. The transistor package of claim 6 , wherein the cladding layer is sintered to the heatsink through the sintered layer.

11. The transistor package of claim 2 , wherein each contact pad is connected to the one or more fins.

12. The transistor package of claim 1 , wherein the transistor package further comprises a semiconductor layer.

13. The transistor package of claim 1 , wherein at least one of the positive busbar or the negative busbar has a flat finger geometry.

14. The transistor package of claim 1 , wherein at least one of the positive busbar or the negative busbar is electrically connected to an AC induction motor.

15. The transistor package of claim 1 , wherein a bend of the “U”-bend shape is in a direction perpendicular to a plane of the encapsulated transistor substrate, and ends before and after the “U”-bend shape are in the same plane as the encapsulated transistor substrate.

16. The transistor package of claim 1 , wherein the positive busbar is a direct current positive busbar or the negative busbar is a direct current negative busbar.

17. An inverter comprising:
a housing, wherein the housing is formed of a metal and is a heat sink, the housing configured to house a plurality of transistor packages;
wherein each of the transistor packages includes:
a transistor substrate, wherein the transistor substrate is directly sintered to the housing through a sintered layer;
an insulated-gate bipolar transistor in thermal contact with the transistor substrate;
an encapsulant that at least partially encapsulates the insulated-gate bipolar transistor;
a Kelvin connection, the Kelvin connection having a first connector directly coupled at a first end to a gate of the insulated-gate bipolar transistor and a second connector directly coupled at a first end to an emitter of the insulated-gate bipolar transistor, wherein the encapsulant further encapsulates a portion of each of the first connector and the second connector, including the first end of the first connector and the first end of the second connector; and
an external busbar connector, the connector having a “U”-bend shape and a busbar connector interconnecting the transistor to either a positive busbar or a negative busbar for providing current to the transistor.

18. The inverter of claim 17 , wherein the insulated-gate bipolar transistor comprises gallium nitride or silicon carbide.

19. The inverter of claim 17 , further comprising a diode in series with the insulated-gate bipolar transistor.

20. The inverter of claim 17 , wherein the sintered layer comprises silver.

21. The inverter of claim 17 , wherein the insulated-gate bipolar transistor comprises silicon.

22. The inverter of claim 17 , wherein the housing comprises fins and contact pads.

Assignees

• Tesla Inc

Inventors

• Liu Wenjun
• Ramm Robert James
• Tepe Alan David
• Campbell Colin Kenneth
• Sasaridis Dino

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/07141

  Means for applying energy, e.g. ovens or lasers · CPC title