SRAM cells with vertical gate-all-round MOSFETs

Patent metadata

Field	Value
Publication number	US-11031073-B2
Application number	US-201715631623-A
Country	US
Kind code	B2
Filing date	Jun 23, 2017
Priority date	Sep 15, 2014
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary.

First claim

What is claimed is:

1. A Static Random Access Memory (SRAM) array comprising:
a plurality of SRAM cells arranged as a plurality of rows and columns, wherein the plurality of SRAM cells comprises a SRAM cell, and the SRAM cell comprises a first pull-up transistor and a first pull-down transistor;
a first continuous active region physically extending into each of the plurality of SRAM cells in a column, wherein the first continuous active region acts as a bit line of the column of the plurality of SRAM cells;
a second continuous active region physically extending into each of the plurality of SRAM cells in the column, wherein the second continuous active region acts as a CVss line of the column of the plurality of SRAM cells;
a third continuous active region physically extending into each of the plurality of SRAM cells in the column, wherein the third continuous active region acts as a CVdd line of the column of the plurality of SRAM cells, wherein the first continuous active region, the second continuous active region, and the third continuous active region are semiconductor regions; and
a gate electrode comprising:
a first portion encircling a first channel region of the first pull-up transistor; and
a second portion encircling a second channel region of the first pull-down transistor, wherein in a top view of the SRAM array, the gate electrode continuously extends from the second continuous active region to the third continuous active region.

2. The SRAM array of claim 1 further comprising:
a fourth continuous active region extending into the column of the plurality of SRAM cells, wherein the fourth continuous active region acts as a complementary bit line of the column of the plurality of SRAM cells.

3. The SRAM array of claim 1 further comprising:
a first, a second, and a third strap line overlapping the first, the second, and the third continuous active regions, respectively, wherein the first, the second, and the third strap lines extend into the column of the plurality of SRAM cells, and are electrically coupled to the first, the second, and the third continuous active regions, respectively.

4. The SRAM array of claim 1 further comprising:
a row of strap cells parallel to, and adjoining, a row of the plurality of SRAM cells, wherein the first, the second, and the third continuous active regions extend into one of the strap cells, and wherein the one of the strap cells electrically connects the first, the second, and the third continuous active regions to an overlying bit line, an overlying CVss line, and an overlying CVdd line in a metal layer.

5. The SRAM array of claim 4 , wherein the row of strap cells does not comprise SRAM cells.

6. The SRAM array of claim 1 further comprising:
a second pull-up transistor and a second pull-down transistor; and
a first pass-gate transistor and a second pass-gate transistor, wherein the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors are vertical transistors electrically coupling with each other to form an SRAM cell in the SRAM array.

7. The SRAM array of claim 6 , wherein the first pass-gate transistor comprises a channel overlapping the first continuous active region.

8. The SRAM array of claim 6 , wherein the first pull-down transistor and the second pull-down transistor comprise channels overlapping the second continuous active region.

9. The SRAM array of claim 6 , wherein the first pull-up transistor and the second pull-up transistor comprise channels overlapping the third continuous active region.

10. The SRAM array of claim 1 , wherein each of the first continuous active region, the second continuous active region, and the third continuous active region is a continuous region that extends into the plurality of SRAM cells in the same column.

11. A Static Random Access Memory (SRAM) array comprising:
a first pull-up transistor and a second pull-up transistor;
a first pull-down transistor and a second pull-down transistor;
a first pass-gate transistor and a second pass-gate transistor, wherein the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors are vertical transistors electrically coupling with each other to form an SRAM cell in the SRAM array;
a first active region acting as both a source/drain region of the first pull-up transistor and a source/drain region of the second pull-up transistor, wherein the first active region is a CVdd power node; and
a second active region acting as both a source/drain region of the first pull-down transistor and a source/drain region of the second pull-down transistor, wherein the second active region is a CVss power node, wherein the first active region and the second active region are semiconductor regions; and
a gate electrode comprising:
a first portion encircling a first channel region of the first pull-up transistor; and
a second portion encircling a second channel region of the first pull-down transistor, wherein the gate electrode continuously extends from the first active region to the second active region.

12. The SRAM array of claim 11 , wherein the SRAM cell has a longer boundary and a shorter boundary intercepting the longer boundary, and the first pull-up transistor, the first pull-down transistor, and the first pass-gate transistor are aligned to a straight line parallel to the longer boundary, wherein the longer boundary is viewed in a top view of the SRAM cell, and the top view is viewed in a direction orthogonal to a plane in which SRAM cells in the SRAM array are spread.

13. The SRAM array of claim 11 , wherein the first pull-up transistor, the first pull-down transistor, and the first pass-gate transistor share a same top plate as a common drain region, wherein the same top plate is a continuous region with no distinguishable interface therein.

14. The SRAM array of claim 11 further comprising:
a third active region extending from a first boundary to a second boundary of the SRAM cell, wherein the third active region acts as a bit line; and
a fourth active region extending from the first boundary to the second boundary, wherein the fourth active region acts a complementary bit line.

15. The SRAM array of claim 11 , wherein the first portion encircles an entire channel region of the first pull-up transistor, and the second portion encircles an entire channel region of the second pull-up transistor.

16. The SRAM array of claim 11 , wherein in a top view of the SRAM array, the gate electrode extends to opposite sides of each of the first active region and the second active region, and wherein the top view is viewed in a direction orthogonal to a plane in which SRAM cells in the SRAM array are spread.

17. A Static Random Access Memory (SRAM) array comprising:
a plurality of SRAM cells arranged as a plurality of rows and a plurality of columns, wherein each of the plurality of SRAM cells comprises:
a first and a second long boundaries parallel to each other;
a first and a second short boundaries parallel to each other, wherein the first and the second short boundaries are shorter than the first and the second long boundaries, and the first and the second long boundaries and the first and the second short boundaries are viewed from a point above a semiconductor substrate toward the semiconductor substrate, with the plurality of SRAM cells formed at a top surface of the semiconductor substrate;
a first continuous active region, a second continuous active region, a thi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title

• H01L29/66666

  Electricity · mapped topic