Semiconductor device

Patent metadata

Field	Value
Publication number	US-11469228-B2
Application number	US-202117146938-A
Country	US
Kind code	B2
Filing date	Jan 12, 2021
Priority date	Apr 20, 2020
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

Disclosed is a semiconductor device comprising a substrate including PMOSFET and NMOSFET regions, first active fins at the PMOSFET region, second active fins at the NMOSFET region, a gate electrode extending in a first direction and running across the first and second active fins, a first source/drain pattern on the first active fins and connecting the first active fins to each other, a second source/drain pattern on the second active fins and connecting the second active fins to each other, a first active contact electrically connected to the first source/drain pattern, and a second active contact electrically connected to the second source/drain pattern. A maximum width of the first active contact in the first direction is less than a maximum width of the second active in the first direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate that includes a PMOSFET region and an NMOSFET region;
a plurality of first active fins at the PMOSFET region;
a plurality of second active fins at the NMOSFET region;
a gate electrode that extends in a first direction and runs across the first active fins and the second active fins;
a first source/drain pattern on the first active fins, the first source/drain pattern connecting the first active fins to each other;
a second source/drain pattern on the second active fins, the second source/drain pattern connecting the second active fins to each other;
a first active contact electrically connected to the first source/drain pattern; and
a second active contact electrically connected to the second source/drain pattern,
wherein a maximum width of the first active contact in the first direction is less than a maximum width of the second active contact in the first direction,
wherein the first active contact is in a region where the first source/drain pattern is recessed,
wherein the second active contact is in a region where the second source/drain pattern is recessed, and
wherein a volume of the region where the first source/drain pattern is recessed is less than a volume of the region where the second source/drain pattern is recessed.

2. The semiconductor device of claim 1 , wherein a ratio of the maximum width of the first active contact in the first direction to the maximum width of the second active contact in the first direction is greater than about 1:4.

3. The semiconductor device of claim 1 , wherein the number of the first active fins is at least three.

4. The semiconductor device of claim 1 , wherein
the first source/drain pattern includes silicon-germanium (SiGe).

5. The semiconductor device of claim 1 , wherein a bottom surface of the first active contact is at a level higher in a direction perpendicular to the substrate than a level of a bottom surface of the second active contact.

6. The semiconductor device of claim 1 , wherein a vertical length of the first active contact is less than a vertical length of the second active contact in a direction perpendicular to the substrate.

7. The semiconductor device of claim 1 , further comprising:
a gate contact electrically connected to the gate electrode,
wherein the gate contact extends in a second direction that intersects the first direction, and
wherein, when viewed in plan view, a portion of the gate contact is between the first active contact and the second active contact and is spaced apart in the first direction from the first active contact and the second active contact.

8. The semiconductor device of claim 1 , further comprising:
a first silicide pattern between the first source/drain pattern and the first active contact; and
a second silicide pattern between the second source/drain pattern and the second active contact.

9. The semiconductor device of claim 8 , wherein
the first active contact has a first sidewall and a second sidewall that face each other in the first direction, and
a portion of the first silicide pattern is in contact with one or both of the first and second sidewalls of the first active contact.

10. A semiconductor device, comprising:
a PMOSFET region and an NMOSFET region that are spaced apart from each other in a first direction on a substrate;
a first active pattern and a second active pattern that are respectively provided on the PMOSFET region and the NMOSFET region;
a first source/drain pattern and a second source/drain pattern that are respectively provided on the first active pattern and the second active pattern; and
a first active contact and a second active contact that are respectively electrically connected to the first source/drain pattern and the second source/drain pattern,
wherein a maximum width of the first active contact in the first direction is less than a maximum width of the second active contact in the first direction,
wherein a ratio of the maximum width of the first active contact in the first direction to the maximum width of the second active contact in the first direction is greater than about 1:4,
wherein a lowermost portion of the first active contact is located at a first level,
wherein a lowermost portion of the second active contact is located at a second level,
wherein the first level is higher than the second level in a direction perpendicular to the substrate,
wherein the first active contact is provided in a region where the first source/drain pattern is recessed,
wherein the second active contact is provided in a region where the second source/drain pattern is recessed, and
wherein a volume of the region where the first source/drain pattern is recessed is less than a volume of the region where the second source/drain pattern is recessed.

11. The semiconductor device of claim 10 , further comprising:
a gate electrode that extends across the first and second active patterns in the first direction; and
a gate contact electrically connected to the gate electrode,
wherein the gate contact extends in a second direction that intersects the first direction, and
wherein, when viewed in plan view, a portion of the gate contact is positioned between the first active contact and the second active contact and is spaced apart in the first direction from the first active contact and the second active contact.

12. The semiconductor device of claim 10 , wherein
the first source/drain pattern includes silicon-germanium (SiGe).

13. The semiconductor device of claim 10 , wherein the first active pattern includes a first active fin, a second active fin, and a third active fin that are arranged along the first direction.

14. The semiconductor device of claim 10 , wherein
a top surface of the first active contact is coplanar with a top surface of the second active contact, and
a vertical length of the first active contact is less than a vertical length of the second active contact in a direction perpendicular to the substrate.

15. The semiconductor device of claim 10 , further comprising:
a first silicide pattern between the first active contact and the first source/drain pattern,
wherein a portion of the first silicide pattern is in contact with one or both of two sidewalls of the first active contact, the two sidewalls facing each other in the first direction.

16. A semiconductor device, comprising:
a logic cell on a substrate, the logic cell including a PMOSFET region and an NMOSFET region that are spaced apart from each other in a first direction;
a device isolation layer that defines a plurality of first active fins at the PMOSFET region and a plurality of second active fins at the NMOSFET region, the first and second active fins extending in a second direction that intersects the first direction;
a first source/drain pattern on the first active fins, the first source/drain pattern connecting the first active fins to each other;
a second source/drain pattern on the second active fins, the second source/drain pattern connecting the second active fins to each other;
a gate electrode that extends in the first direction and extends across the first active fins and the second active fins;
a gate spacer on opposite sides of the gate electrode, the gate spacer extending in the first direction;
a gate dielectric pattern between the gate electrode and the first active fin, between the gate electrode and the second active fin, and between the gate electrode and the gate spacer;
a gate capping pattern on a top surface of the gate electrode, the gate capping patt

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Chanwook
• Kim Seungkwon
• Kim Jaechul
• Ko Younggun
• Masuoka Yuri

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L29/45

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic