Contact resistance mitigation

Patent metadata

Field	Value
Publication number	US-9875332-B2
Application number	US-201514851644-A
Country	US
Kind code	B2
Filing date	Sep 11, 2015
Priority date	Sep 11, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Various implementations described herein are directed to systems and methods for mitigating contact resistance. In one implementation, a method may include analyzing operating conditions for cells of an integrated circuit. The method may include selectively marking instances of the cells having timing degradation along a critical path of the integrated circuit. The method may include reducing contact resistance for the selectively marked instances of the cells having timing degradation.

First claim

What is claimed is:

1. A method, comprising:
analyzing operating conditions for cells of an integrated circuit;
selectively marking instances of the cells having timing degradation along a critical path of the integrated circuit;
reducing contact resistance for the selectively marked instances of the cells having timing degradation, wherein the selectively marked instances of the cells comprise selectively marked transistors, and wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by increasing an area of the contacts for the selectively marked transistors, including increasing an area of the contact of a selectively marked transistor to overlap a gate proximate to the selectively marked transistor; and
fabricating a mask based upon the instances of the cells of the integrated circuit.

2. The method of claim 1 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by providing a higher drive current to the selectively marked transistors.

3. The method of claim 1 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by modifying implants for the contacts of the selectively marked transistors.

4. The method of claim 1 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by providing different lithographic bias on gate contact depositions for the selectively marked transistors.

5. The method of claim 1 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by providing different source/drain implants for the selectively marked transistors.

6. The method of claim 1 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by providing different silicide depositions for the selectively marked transistors.

7. The method of claim 1 , wherein reducing the contact resistance further comprises modifying contacts of the selectively marked transistors by removing at least one gate that is adjacent to at least one of the selectively marked transistors.

8. The method of claim 1 , wherein reducing the contact resistance comprises increasing area of the contacts for the selectively marked transistors by physically widening the contacts for the selectively marked transistors.

9. The method of claim 8 , wherein increasing the area of the contacts for the selectively marked transistors comprises reducing a vertical length of the physically wider contacts for the selectively marked transistors.

10. The method of claim 1 , wherein reducing the contact resistance comprises increasing area of the vias for the selectively marked transistors by physically widening the vias for the selectively marked transistors.

11. A non-transitory computer-readable medium having stored thereon a plurality of computer-executable instructions which, when executed by a computer, cause the computer to:
analyze timing data associated with cells of an integrated circuit;
selectively mark transistors of the cells having timing degradation along one or more paths of the integrated circuit; and
increase drive current of contacts for the selectively marked transistors of the cells having timing degradation by reducing contact resistance of the contacts, wherein reducing the contact resistance of the contacts comprises increasing an area of the contacts for the selectively marked transistors, including increasing an area of the contact of a selectively marked transistor to overlap a gate proximate to the selectively marked transistor.

12. The computer-readable medium of claim 11 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by providing different voltage threshold implants for the selectively marked transistors.

13. The computer-readable medium of claim 11 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by providing different lithographic bias on gate contact depositions for the selectively marked transistors.

14. The computer-readable medium of claim 11 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by providing different source/drain implants for the selectively marked transistors.

15. The computer-readable medium of claim 11 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by providing different silicide depositions for the selectively marked transistors.

16. The computer-readable medium of claim 11 , wherein increasing the area of the contacts for the selectively marked transistors comprises physically widening the contacts for the selectively marked transistors.

17. The computer-readable medium of claim 16 , wherein increasing the area of the contacts for the selectively marked transistors comprises reducing the vertical length of the physically wider contacts for the selectively marked transistors.

18. The computer-readable medium of claim 11 , wherein reducing the contact resistance comprises modifying contacts of the selectively marked transistors by increasing area of vias associated with the contacts for the selectively marked transistors.

19. A system, comprising:
a processor; and
memory having stored thereon instructions that, when executed by the processor, cause the processor to:
analyze timing data associated with operating conditions of cells along one or more paths of an integrated circuit;
selectively mark instances of the cells showing timing degradation; and
reduce contact resistance of contacts for the selectively marked instances of the cells showing timing degradation by increasing an area of the contacts for the selectively marked instances of the cells, including increasing an area of the contact of a selectively marked instance of the cells to overlap a gate instance proximate to the selectively marked instance of the cells.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Yeric Gregory Munson

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title