Use of contacts to create differential stresses on devices

Patent metadata

Field	Value
Publication number	US-9196528-B2
Application number	US-201313798643-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Sep 28, 2010
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

First claim

What is claimed is:

1. An integrated circuit (IC) chip comprising:
a substrate having a p-type field effect transistor (PFET) and a n-type field effect transistor (NFET) thereon, the PFET and NFET each including a sourcedrain region;
a PFET contact to a source/drain region of the PFET;
an NFET contact to a source/drain region of the NFET; and
a silicide layer disposed over the PFET and the NFET, wherein the silicide layer is absent from a portion of the upper surface of each of the PFET and the NFET immediately adjacent a gate in each of the PFET and the NFET;
wherein only one of:
the PFET contact extends through a full thickness of the silicide layer and into the source/drain region of the PFET, or
the NFET contact extends through a full thickness of the silicide layer and into the source/drain region of the NFET,

wherein in the case that the PFET contact extends into the source/drain region of the PFET, the PFET contact includes a silicon germanium layer between the PFET contact and the source/drain region of the PFET.

2. The IC chip of claim 1 , wherein in the case that the PFET contact extends into the source/drain region of the PFET, the PFET contact comprises one of the following materials: nickel (Ni), Platinum (Pt), palladium (Pd), titanium (Ti) or cobalt (Co).

3. The IC chip of claim 1 , wherein the silicon germanium layer imparts a compressive stress on the PFET.

4. The IC chip of claim 1 , wherein in the case that the NFET contact extends into the source/drain region of the NFET, the NFET contact comprises one of the following materials: tungsten (W), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) or copper (Cu).

5. The IC chip of claim 1 , wherein one of: the PFET contact extends approximately 50 to approximately 3000 angstroms into the source/drain region of the PFET and the NFET contact extends approximately 50 to approximately 3000 angstroms into the source/drain region of the NFET.

6. The IC chip of claim 1 , further comprising a nitride layer disposed over the substrate and at least one of the PFET or the NFET.

7. The IC chip of claim 6 , wherein the nitride layer is between 50 Angstroms and 3,000 Angstroms in thickness.

8. The IC chip of claim 6 , further comprising a dielectric layer disposed over the nitride layer.

9. The IC chip of claim 8 , wherein the dielectric layer is between approximately 200 Angstroms and approximately 20,000 Angstroms in thickness.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Ellis-Monaghan John J
• Gambino Jeffrey P
• Peterson Kirk D
• Rankin Jed H
• Robison Robert R

Classifications

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10D84/8312

  the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title