Substrate processing device

Patent metadata

Field	Value
Publication number	US-11469127-B2
Application number	US-202016931723-A
Country	US
Kind code	B2
Filing date	Jul 17, 2020
Priority date	Sep 12, 2019
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A substrate processing device according to the present embodiment includes a processing tank configured to be capable of accumulating a liquid. A conveyer can array a plurality of semiconductor substrates in such a manner that front surfaces of the semiconductor substrates face a substantially horizontal direction, and transport the semiconductor substrates into the processing tank. A plurality of liquid suppliers can supply the liquid toward an inside of the processing tank from a lower portion of the processing tank. A plurality of current plates are arranged on at least either one end side or the other end side of an array of the semiconductor substrates. The current plates are provided in a first gap region above the semiconductor substrates in gaps between the conveyer and a sidewall of the processing tank on both sides of the conveyer as viewed from an array direction of the semiconductor substrates.

First claim

The invention claimed is:

1. A substrate processing device comprising:
a processing tank configured to be capable of accumulating a liquid;
a conveyer configured to be capable of arraying a plurality of semiconductor substrates in such a manner that front surfaces of the semiconductor substrates face a substantially horizontal direction, and transporting the semiconductor substrates into the processing tank;
a plurality of liquid suppliers configured to be capable of supplying the liquid toward an inside of the processing tank from a lower portion of the processing tank; and
a plurality of current plates being arranged on at least either one end side or the other end side of an array of the semiconductor substrates, the current plates being provided in a first gap region above the semiconductor substrates in gaps between the conveyer and a sidewall of the processing tank on both sides of the conveyer as viewed from an array direction of the semiconductor substrates, wherein
the conveyer transports the semiconductor substrates into or out of the processing tank by moving the semiconductor substrates up or down, and
the current plates are provided at locations where the current plates are not in contact with the conveyer and the semiconductor substrates.

2. The substrate processing device according to claim 1 , wherein upper ends of the current plates are positioned at locations equal to or higher than an upper end of the processing tank.

3. The substrate processing device according to claim 1 , wherein the current plates are provided to obstruct the first gap region as viewed from the array direction of the semiconductor substrates.

4. The substrate processing device according to claim 1 , wherein
the current plates are arranged on one end side of the array of the semiconductor substrates, and
a distance between a semiconductor substrate adjacent to the current plates on the one end side of the array of the semiconductor substrates and the current plates along the array direction of the semiconductor substrates has a value from an interval between the semiconductor substrates to twice as large as the interval.

5. The substrate processing device according to claim 1 , wherein
the current plates comprise:
a first current plate and a second current plate arranged on one end side of the array of the semiconductor substrates and respectively arranged on both sides of the conveyer as viewed from the array direction of the semiconductor substrates; and
a third current plate and a fourth current plate arranged on the other end side of the array of the semiconductor substrates and respectively arranged on both sides of the conveyer as viewed from the array direction of the semiconductor substrate.

6. The substrate processing device according to claim 5 , wherein a distance between a semiconductor substrate adjacent to the first and second current plates on the one end side of the array of the semiconductor substrate and the first and second current plates along the array direction of the semiconductor substrates has a value from an interval between the semiconductor substrates to twice as large as the interval.

7. The substrate processing device according to claim 6 , wherein a distance between a semiconductor substrate adjacent to the third and fourth current plates on the other end side of the array of the semiconductor substrates and the third and fourth current plates along the array direction of the semiconductor substrates has a value from the interval of the semiconductor substrates to twice as large as the interval.

8. The substrate processing device according to claim 1 , wherein the current plates have a substantially same shape and are provided at a substantially same height.

9. The substrate processing device according to claim 1 , wherein
the first gap region is located above substantial centers of the semiconductor substrates, and
lower ends of the current plates are at height locations near centers of the semiconductor substrates.

10. The substrate processing device according to claim 1 , wherein portions of lower ends of the current plates have a substantially arc shape corresponding to an outer edge of the semiconductor substrates.

11. The substrate processing device according to claim 1 , wherein
the conveyer comprises a support supporting the semiconductor substrates from below, and a conveyer plate connecting with the support and facing the semiconductor substrates, and
the conveyer plate has an opening to include an intersecting position of supply directions of the liquid supplied from the liquid suppliers as viewed from the array direction of the semiconductor substrates.

12. The substrate processing device according to claim 1 , wherein
the conveyer comprises a support supporting the semiconductor substrates from below, and a conveyer plate connecting with the support and facing the semiconductor substrates, and
the substrate processing device further comprises a fifth current plate provided on an opposite side of the array of the semiconductor substrates to the conveyer plate.

13. The substrate processing device according to claim 12 , wherein the fifth current plate is arranged between the current plates as viewed from the array direction of the semiconductor substrates.

14. The substrate processing device according to claim 12 , wherein an upper side of the fifth current plate is positioned above a liquid level in the processing tank during processing of the semiconductor substrates.

15. The substrate processing device according to claim 12 , further comprising a sixth current plate provided on a side of the conveyer plate with respect to the array of the semiconductor substrates.

16. The substrate processing device according to claim 15 , wherein the sixth current plate is arranged between the current plates as viewed from the array direction of the semiconductor substrates.

17. The substrate processing device according to claim 1 , wherein the conveyer opens side portions of the semiconductor substrates in directions orthogonal to the array direction of the semiconductor substrates in a substantially horizontal plane.

18. The substrate processing device according to claim 1 , wherein the semiconductor substrates are arrayed in such a manner that element formation surfaces of semiconductor substrates in each pair of adjacent semiconductor substrates face each other.

19. The substrate processing device according to claim 1 , further comprising a plurality of gas suppliers configured to supply gas bubbles from below the semiconductor substrates.

20. The substrate processing device according to claim 1 , wherein planes of the current plates, which obstruct the first gap region between the conveyer and the sidewall of the processing tank, face in a direction perpendicular to a direction in which a plane of the sidewall faces.

Assignees

• Kioxia Corp

Inventors

• Kinoshita Shigeru
• Matsumoto Shusaku
• Kawano Koichiro
• Fujita Hiroshi
• Kitamura Yoshinori

Classifications

• H10P72/0426 Primary

  with the semiconductor substrates being dipped in baths or vessels · CPC title

• H10P72/0416

  with the semiconductor substrates being dipped in baths or vessels · CPC title

• H10P72/15

  Horizontal carrier comprising wall type elements whereby the substrates are vertically supported, e.g. comprising sidewalls · CPC title

• H10P72/3312 Primary

  Vertical transfer of a batch of workpieces · CPC title

• H10P72/0406

  for cleaning followed by drying, rinsing, stripping, blasting or the like · CPC title