Detection of an incorrectly located read voltage

Patent metadata

Field	Value
Publication number	US-11468959-B2
Application number	US-202117313939-A
Country	US
Kind code	B2
Filing date	May 6, 2021
Priority date	May 7, 2020
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).

First claim

What is claimed is:

1. A device, comprising:
a group of memory cells, each configured to store more than one bit of data; and
a logic circuit configured to:
identify a plurality of voltages to read the group of memory cells;
determine, in the group of memory cells, a count of first memory cells each having a threshold voltage higher than the plurality of voltages;
compare the count of the first memory cells with a predetermined range of a fraction of memory cells in the group; and
determine, based on a result of comparing the count and the predetermined range, whether the plurality of voltages are erroneous.

2. The device of claim 1 , further comprising:
at least one integrated circuit die;
a plurality of groups of memory cells, including the group of memory cells, formed on the at least one integrated circuit die; and
an integrated circuit package configured to enclose the device.

3. The device of claim 2 , wherein the group of memory cells comprises multiple pages of memory cells.

4. The device of claim 2 , further comprising:
a calibration circuit configured to:
read the group of memory cells at a plurality of test voltages in a test voltage range;
determine a bit count at each respective test voltage among the plurality of test voltages, wherein the bit count at the respective test voltage identifies a number of memory cells in the group that, when read at the respective test voltage, provide a predetermined bit value; and
compute a voltage to read the group of memory cells based on the bit count at the each respective voltage among the plurality of test voltages.

5. The device of claim 4 , wherein the calibration circuit is further configured to:
compute a count difference between bit counts at each pair of adjacent test voltage voltages among the plurality of test voltages, wherein the voltage to read the group of memory cells is computed based on the count difference.

6. The device of claim 5 , wherein the plurality of test voltages are evenly distributed in the test voltage range.

7. The device of claim 6 , wherein the calibration circuit is configured to read the group of memory cells at test voltages in a plurality of non-overlapping test voltage ranges respectively for the plurality of voltages to read the group of memory cells.

8. The device of claim 7 , wherein based on the count of the first memory cells being outside of the predetermined range, the logic circuit is configured to determine that at least one of the plurality of non-overlapping test voltage ranges is incorrectly positioned for calibration of the plurality of voltages to read the group of memory cells.

9. The device of claim 8 , wherein in response to the count of the first memory cells being outside of the predetermined range, the logic circuit is configured to search for a test voltage range for calibration of a voltage to read the group of memory cells.

10. The device of claim 8 , wherein in response to the count of the first memory cells being outside of the predetermined range, the logic circuit is configured to generate a response to cause a search for a test voltage range for calibration of a voltage to read the group of memory cells.

11. A method, comprising:
identifying, by a logic circuit of a device having a group of memory cells, a plurality of voltages to read the group of memory cells formed on an integrated circuit die;
determining, by the logic circuit in the device, within the group of memory cells, a count of first memory cells each having a threshold voltage higher than the plurality of voltages;
comparing, by the logic circuit in the device, the count of the first memory cells with a predetermined range; and
determining, by the logic circuit in the device, based on the comparing of the count with the predetermined range, whether the plurality of voltages are erroneous.

12. The method of claim 11 , further comprising:
reading the group of memory cells at a plurality of test voltages in a test voltage range;
determining a bit count at each respective test voltage among the plurality of test voltages, wherein the bit count at the respective test voltage identifies a number of memory cells in the group that, when read at the respective test voltage, provide a predetermined bit value; and
computing a voltage to read the group of memory cells based on the bit count at the each respective voltage among the plurality of test voltages.

13. The method of claim 12 , further comprising:
computing a count difference between bit counts at each pair of adjacent test voltages among the plurality of test voltages, wherein the voltage to read the group of memory cells is computed based on the count difference.

14. The method of claim 13 , wherein the plurality of test voltages are evenly distributed in the test voltage range.

15. The method of claim 14 , further comprising:
reading the group of memory cells at test voltages in a plurality of non-overlapping test voltage ranges respectively for the plurality of voltages to read the group of memory cells;
wherein based on the count of the first memory cells being outside of the predetermined range, at least one of the plurality of non-overlapping test voltage ranges is determined to be incorrectly positioned for calibration of the plurality of voltages to read the group of memory cells.

16. The method of claim 15 , further comprising:
searching, in response to the count of the first memory cells being outside of the predetermined range, for a test voltage range for calibration of a voltage to read the group of memory cells.

17. The method of claim 15 , further comprising:
generating, in response to the count of the first memory cells being outside of the predetermined range, a response to a command, the response configured to cause a search for a test voltage range for calibration of a voltage to read the group of memory cells.

18. A system, comprising:
a processing device; and
a memory device having a plurality of groups of memory cells and a logic circuit;
wherein, in response to a command from the processing device identifying a group of memory cells among the plurality of groups, the logic circuit is configured to:
identify a plurality of voltages to read the group of memory cells at a plurality of voltage levels respectively to retrieve data from the group of memory cells;
determine, among the group of memory cells, a count of first memory cells each having a threshold voltage higher than the plurality of voltages;
compare the count of the first memory cells with a predetermined range; and
determine, based on a result of comparing the count with the predetermined range, whether the plurality of voltages are erroneous.

19. The system of claim 18 , wherein to determine each respective voltage in the plurality of voltages, the memory device is configured to:
read the group of memory cells at a plurality of test voltages in a respective test voltage range corresponding to a respective voltage level among the plurality of voltage levels;
determine a bit count at each respective test voltage among the plurality of test voltages, wherein the bit count at the respective test voltage identifies a number of memory cells in the group that, when read at the respective test voltage, provide a predetermined bit value; and
compute the respective voltage to read the group of memory cells at the respective voltage level based on the bit count at the each respective voltage among the plurality of test voltages.

20. The system of claim 18 , where

Assignees

• Micron Technology Inc

Inventors

• Parthasarathy Sivagnanam
• Fitzpatrick James
• Khayat Patrick Robert
• Alhussien Abdelhakim S

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/20

  using counters or linear-feedback shift registers [LFSR] · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title