Dynamic valley searching in solid state drives

Patent metadata

Field	Value
Publication number	US-11468953-B2
Application number	US-202117197488-A
Country	US
Kind code	B2
Filing date	Mar 10, 2021
Priority date	Mar 10, 2021
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.

First claim

What is claimed is:

1. A storage device, comprising:
a controller configured to direct the storage device to:
perform initial searching reads on data requiring access to multiple planes of memory simultaneously, wherein:
a plurality of memory states for calibration are determined;
a plurality of threshold valleys between the memory states are determined;
a unique memory state is assigned to each of the plurality of planes for performing searching reads; and
a series of searching reads and valley scans are performed on the plurality of planes; and
generate calibration data based on the initial searching reads.

2. The storage device of claim 1 , wherein, in response to a received host read command, the calibration data is utilized by one or more read sensors to reduce read error rates.

3. The storage device of claim 1 , wherein, in response to a predetermined threshold being surpassed, the calibration data is utilized by one or more read sensors to reduce read error rates.

4. The storage device of claim 3 , wherein the predetermined threshold is associated with a number of write cycles correlating to fifty percent of the storage device lifespan.

5. The storage device of claim 1 , wherein the storage device utilizes a multi-pass programming method to store data within a plurality of memory devices configured on a plurality of planes and is configured to perform a calibrated read on the data requiring access to multiple planes of memory simultaneously, wherein each of the plurality of planes utilizes the generated calibration data to calibrate the read sensors for each memory state prior to read.

6. The storage device of claim 5 , wherein the generated calibration data comprises at least calibration data associated with the memory states assigned to the plurality of planes.

7. The storage device of claim 6 , wherein the calibration data is pooled to comprise data associated with each of the memory states assigned to the plurality of planes for searching reads.

8. The storage device of claim 7 , wherein the calibrated read utilizes the pooled calibration data.

9. The storage device of claim 8 , wherein the pooled calibration data is utilized during the calibrated read to provide calibration settings for each of the plurality of memory states to each of the plurality of planes.

10. The storage device of claim 9 , wherein the storage device is configured to provide minimal memory read variation between planes.

11. The storage device of claim 10 , wherein each of the plurality of planes may perform a calibrated read utilizing calibration data entirely derived from one or more separate planes.

12. The storage device of claim 1 , wherein the series of searching reads are done prior to the series of valley scans.

13. The storage device of claim 1 , wherein the series of valley searches are done alternating with the series of searching reads.

14. The storage device of claim 13 , wherein the alternation comprises performing a searching read at a first voltage which is then followed by a valley read at an associated valley.

15. A storage device, comprising:
a controller configured to direct the storage device to:
perform initial searching reads on data requiring access to multiple planes of memory simultaneously, wherein:
a plurality of memory states for calibration are determined;
a plurality of threshold valleys between the memory states are determined;
a unique memory state is assigned to each of the plurality of planes for performing searching reads;
a series of searching reads and valley scans are performed on the plurality of planes;
wherein the valley scans can be performed at a variable resolution; and
generate calibration data based on the initial searching reads.

16. The storage device of claim 15 , wherein the valley scan resolution is increased to provide an increased accuracy in reads.

17. The storage device of claim 15 , wherein the variability of the valley scan resolutions is dynamically adjusted based on one or more predetermined thresholds.

Assignees

• Western Digital Tech Inc

Inventors

• Singidi Harish
• Banerjee Amiya
• Gupta Shantanu

Classifications

• G11C2029/0409

  Online test · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title