Display apparatus

US11468812B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11468812-B2
Application numberUS-202117366445-A
CountryUS
Kind codeB2
Filing dateJul 2, 2021
Priority dateAug 25, 2020
Publication dateOct 11, 2022
Grant dateOct 11, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display apparatus comprises a display panel on which a plurality of pixels are displayed, a plurality of signal lines to which a signal required to drive the display panel is supplied, and an electrostatic discharge circuit connected between each of the plurality of signal lines and the electrostatic discharge line. The electrostatic discharge circuit includes first and second current paths between the signal line and the electrostatic discharge line, a first electrostatic discharge circuit connected to the first current path, including a plurality of first thin film transistors having a first gate electrode connected to the second current path and a second gate electrode connected to the first current path, and a second electrostatic discharge circuit connected to the second current path, including at least one second thin film transistor having a first gate electrode connected to the first current path and a second gate electrode connected to the first current path.

First claim

Opening claim text (preview).

What is claimed is: 1. A display apparatus comprising: a display panel on which a plurality of pixels are displayed; a plurality of signal lines to which a signal to drive the display panel is supplied; and an electrostatic discharge circuit connected between each of the plurality of signal lines and the electrostatic discharge line, wherein the electrostatic discharge circuit includes: first and second current paths between the signal line and the electrostatic discharge line; a first electrostatic discharge circuit connected to the first current path and including a plurality of first thin film transistors having a first gate electrode connected to the second current path and a second gate electrode connected to the first current path; and a second electrostatic discharge circuit connected to the second current path and including at least one second thin film transistor having a first gate electrode connected to the first current path and a second gate electrode connected to the first current path. 2. The display apparatus of claim 1 , wherein the plurality of signal lines include at least one of: gate lines connected with each of the plurality of pixels; data lines connected with each of the plurality of pixels; or gate control lines between a gate driver for supplying a scan signal to the gate lines and a controller for controlling the gate driver. 3. The display apparatus of claim 1 , wherein each of the first and second thin film transistors includes one or more of first and second unit thin film transistors comprised of two sub thin film transistors connected in series. 4. The display apparatus of claim 1 , wherein the second gate electrode of the first thin film transistors and the second gate electrode of the second thin film transistors are light shields. 5. The display apparatus of claim 3 , wherein the sub thin film transistor includes a double gate coplanar type. 6. The display apparatus of claim 3 , wherein the first unit thin film transistor includes: a first sub thin film transistor disposed at a side of the signal line; and a second sub thin film transistor disposed at a side of the electrostatic discharge line, and a first gate electrode of each of the first and second sub thin film transistors is connected to the second current path, and a second gate electrode of each of the first and second sub thin film transistors is connected to the first current path. 7. The display apparatus of claim 6 , wherein the second gate electrode of the first sub thin film transistor is connected to a first source/drain electrode of the first thin film transistor, and the second gate electrode of the second sub thin film transistor is connected to a second source/drain electrode of the second thin film transistor. 8. The display apparatus of claim 6 , wherein a first source/drain of the first sub thin film transistor is connected to the first source/drain electrode of the first thin film transistor, a second source/drain of the second sub thin film transistor is connected to the second source/drain electrode of the first thin film transistor, and a second source/drain of the first sub thin film transistor is connected to a first source/drain of the second sub thin film transistor. 9. The display apparatus of claim 8 , wherein an area between a channel portion of the first sub thin film transistor and a channel portion of the second sub thin film transistor constitutes the second source/drain of the first sub thin film transistor and the first source/drain of the second sub thin film transistor. 10. The display apparatus of claim 3 , wherein the second unit thin film transistor includes: a first sub thin film transistor disposed at a side of the signal line; and a second sub thin film transistor disposed at a side of the electrostatic discharge line, and wherein the first gate electrode of each of the first and second sub thin film transistors is connected to the first current path, and the second gate electrode of the first and second sub thin film transistors is connected to the second current path. 11. The display apparatus of claim 10 , wherein the second gate electrode of the first sub thin film transistor is connected to the first source/drain electrode of the second thin film transistor, and the second gate electrode of the second sub thin film transistor is connected to the second source/drain electrode of the second thin film transistor. 12. The display apparatus of claim 10 , wherein the first source/drain of the first sub thin film transistor is connected to the first source/drain electrode of the second thin film transistor, the second source/drain of the second sub thin film transistor is connected to the second source/drain electrode of the second thin film transistor, and the second source/drain of the first sub thin film transistor is connected to the first source/drain of the second sub thin film transistor. 13. The display apparatus of claim 12 , wherein an area between a channel portion of the first sub thin film transistor and a channel portion of the second sub thin film transistor constitutes the second source/drain of the first sub thin film transistor and the first source/drain of the second sub thin film transistor. 14. The display apparatus of claim 3 , wherein the first thin film transistor includes even number of first unit thin film transistors connected in series, the first gate electrode of each of all the sub thin film transistors included in the first thin film transistor is connected to the second current path, and the second gate electrode of each of all the sub thin film transistors included in the first thin film transistor is connected to the first current path. 15. The display apparatus of claim 4 , wherein a second gate electrode of each of sub thin film transistors of ½ number of first unit thin film transistor disposed at a side of the signal line is connected to the first source/drain electrode of the first thin film transistor, and a second gate electrode of each of sub thin film transistors of ½ number of first unit thin film transistor at a side of the electrostatic discharge line is connected to the second source/drain of the first thin film transistor. 16. The display apparatus of claim 3 , wherein the second thin film transistor includes even number of second unit thin film transistors connected in series, the first gate electrode of each of all the sub thin film transistors included in the second thin film transistor is connected to the first current path, and the second gate electrode of each of all the sub thin film transistors included in the second thin film transistor is connected to the second current path. 17. The display apparatus of claim 16 , wherein a second gate electrode of each of sub thin film transistors of ½ number of second unit thin film transistor at a side of the signal line is connected to the first source/drain electrode of the second thin film transistor, and a second gate electrode of each of sub thin film transistors of ½ number of second unit thin film transistor at a side of the electrostatic discharge line is connected to the second source/drain of the second thin film transistor. 18. The display apparatus of claim 7 , wherein the first source/drain electrode is a source/drain electrode dispose at a side of the signal line, and the second source/drain electrode is a source/drain electrode disposed at a side of the electrostatic discharge line. 19. The display apparatus of claim 1 , wherein the first electrostatic discharge circuit includes n number of

Assignees

Inventors

Classifications

  • G09G3/20Primary

    for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

  • Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

  • Display protection · CPC title

  • Structural and physical details of display devices · CPC title

  • adapted to a particular application and not provided for elsewhere · CPC title

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What does patent US11468812B2 cover?
A display apparatus comprises a display panel on which a plurality of pixels are displayed, a plurality of signal lines to which a signal required to drive the display panel is supplied, and an electrostatic discharge circuit connected between each of the plurality of signal lines and the electrostatic discharge line. The electrostatic discharge circuit includes first and second current paths b…
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/20. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 11 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).