Electrostatic discharge circuit and liquid crystal display device including the same

Patent metadata

Field	Value
Publication number	US-9772532-B2
Application number	US-201514643756-A
Country	US
Kind code	B2
Filing date	Mar 10, 2015
Priority date	Mar 10, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a transistor structure having at least five thin film transistors (TFTs), said transistor structure configured in view of changes in operating characteristics that depend on a channel length of a back channel etched (BCE) type oxide transistor.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) circuit comprising a transistor structure having at least five thin film transistors (TFTs), said transistor structure being configured in view of changes in operating characteristics that depend on a channel length of a back channel etched (BCE) type oxide transistor.

2. The ESD circuit of claim 1 , wherein said transistor structure comprises:
at least three switching thin film transistors (TFTs), each being an oxide TFT of a BCE type with an active layer of oxide; and
at least two equalizer thin film transistors (TFTs), operatively connected with said switching TFTs, each equalizer TFT being an oxide TFT of a BCE type with an active layer of oxide and having a sequence of two or more oxide TFTs being connected together in series to achieve an effective channel length that is greater than a channel length of a single oxide TFT.

3. The ESD circuit of claim 2 , wherein said equalizer TFTs comprises:
a first equalizer TFT having one end connected to a first switching TFT and having its other end connected to a second switching TFT, and
a second equalizer TFT having one end connected to said second switching TFT and having its other end connected to a third switching TFT.

4. The ESD circuit of claim 2 , wherein said sequence of two or more oxide TFTs share one gate electrode.

5. The ESD circuit of claim 2 , wherein all of said switching TFTs and said equalizer TFTs are located in a non-active area of a display panel.

6. The ESD circuit of claim 5 , wherein each switching TFT and each oxide TFT in each equalizer TFT have the same structure as that of oxide TFTs in an active area of said display panel due to the same manufacturing process thereof.

7. The ESD circuit of claim 6 , each oxide TFT in each equalizer TFT has the same channel length as oxide TFTs in said active area of said display panel.

8. The ESD circuit of claim 6 , each oxide TFT in each equalizer TFT has substantially the same operating characteristic as oxide TFTs in said active area of said display panel.

9. An apparatus comprising:
a display panel having an active area including an array of pixels and having a non-active area surrounding the active area, with each pixel connected to at least one among a plurality of data lines, connected to at least one among a plurality of gate lines, and including one or more oxide thin film transistors (TFTs) that employ oxide as its active layer; and
a plurality of electrostatic protection elements in the non-active area that inhibit electrostatic charges from flowing into the active area via the data lines or the gate lines,
each electrostatic protection element including a plurality of oxide TFTs among which at least two oxide TFTs are center TFTs that respectively have an amalgamated structure with three of more individual oxide TFTs connected in series to attain an elongated effective channel length.

10. The apparatus of claim 9 , the electrostatic protection elements comprising:
a first set of electrostatic protection circuits disposed at start portions and end portions of each of the gate lines and of each of the data lines; and
a second set of electrostatic protection circuits disposed between a common voltage line and the first set of electrostatic protection circuits.

11. The apparatus of claim 10 , wherein the second set of electrostatic protection circuits includes:
a data protection circuit respectively disposed at each lower corner of the display panel, a first terminal thereof connected to the common voltage line and a second terminal thereof connected to ground, to protect the display panel from overvoltage currents.

12. The apparatus of claim 11 , wherein the electrostatic protection elements including the plurality of oxide TFTs achieve a 5-TFT configuration comprising:
a first center TFT having one end connected to a first switching TFT and having its other end connected to a second switching TFT, and a second center TFT having one end connected to said second switching TFT and having its other end connected to a third switching TFT.

13. A display device comprising:
a pixel disposed in an active area of a display panel; and
an electrostatic discharge (ESD) circuit disposed in a non-active area of the display panel,
wherein,
the ESD circuit comprises a first thin film transistor (TFT) configured to prevent a current from simultaneously flowing in two directions and a second TFT configured to divert an overvoltage current, and
a channel length of the first TFT differs from a channel length of the second TFT.

14. The display device of claim 13 , wherein,
the channel length of the first TFT is equal to a channel length of a TFT disposed in the pixel, and
the channel length of the second TFT is longer than the channel length of the TFT disposed in the pixel.

15. The display device of claim 14 , wherein a channel of the second TFT comprises two or more channels which have the same length as a length of a channel of the TFT disposed in the pixel and are serially connected to each other.

16. The display device of claim 14 , wherein,
the ESD circuit comprises three first TFTs and two second TFTs, and
each of the two second TFTs is disposed between two first TFTs.

17. The display device of claim 16 , wherein each of the three first TFTs, the two second TFTs, and the TFT disposed in the pixel is a back channel etched (BCE) type oxide TFT.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Sang Woon
• Yu Sang Hee
• Jeong Hoon

Classifications

• H01L27/0266

  Electricity · mapped topic

• G09G2330/04

  Display protection · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G02F1/136204 Primary

  Arrangements to prevent high voltage or static electricity failures · CPC title

• H10D89/811

  using FETs as protective elements · CPC title