Integrated circuit with electrostatic discharge protection
US-2024395801-A1 · Nov 28, 2024 · US
US9515064B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9515064-B2 |
| Application number | US-201414314808-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 25, 2014 |
| Priority date | Jul 1, 2013 |
| Publication date | Dec 6, 2016 |
| Grant date | Dec 6, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
In a static electricity protection circuit according to the invention, a first wiring is electrically connected to a drain of a first p-type transistor and a gate and a source of a first n-type transistor; a second wiring is electrically connected to a gate and a source of the first p-type transistor, a drain of the first n-type transistor, a drain of a second p-type transistor and a gate and a source of a second n-type transistor; and a third wiring is electrically connected to a gate and a source of the second p-type transistor and a drain of the second n-type transistor.
Opening claim text (preview).
What is claimed is: 1. A static electricity protection device comprising: a first p-type transistor; a first n-type transistor; a second p-type transistor; a second n-type transistor; a low electric potential wiring supplied with a first electric potential; a signal wiring supplied with a second electric potential higher than the first electric potential; and a high electric potential wiring supplied with a third electric potential higher than both the first electric potential and the second electric potential, wherein the first electric potential is supplied to one of a source and a drain of the first p-type transistor, a gate of the first n-type transistor, and one of a source and a drain of the first n-type transistor, through the low electric potential wiring, the second electric potential is supplied to a gate of the first p-type transistor, the other one of the source and the drain of the first p-type transistor, the other one of the source and the drain of the first n-type transistor, one of a source and a drain of the second p-type transistor, a gate of the second n-type transistor, and one of a source and a drain of the second n-type transistor, through the signal wiring, the third electric potential is supplied to a gate of the second p-type transistor, the other one of the source and the drain of the second p-type transistor and the other one of the source and the drain of the second n-type transistor, through the high electric potential wiring, and the signal wiring is disposed between the low electric potential wiring and the high electric potential wiring. 2. The static electricity protection device according to claim 1 , wherein an amount of capacitance of the low electric potential wiring and an amount of capacitance of the high electric potential wiring are each larger than an amount of capacitance of the signal wiring. 3. An electro-optic device comprising the static electricity protection device according to claim 1 . 4. An electronic device comprising the static electricity protection device according to claim 1 . 5. An electronic device comprising the electro-optic device according to claim 3 . 6. The static electricity protection device according to claim 1 , wherein the gate of the first p-type transistor is connected to the gate of the second n-type transistor as a same layer wiring. 7. The static electricity protection device according to claim 1 , wherein an on-state electric current of the first p-type transistor is the same as a current of the second p-type transistor. 8. The static electricity protection device according to claim 1 , wherein an on-state electric current of the first n-type transistor is the same as a current of the second n-type transistor. 9. The static electricity protection device according to claim 1 , wherein a channel length of the first p-type transistor is the same as a channel length of the second p-type transistor. 10. The static electricity protection device according to claim 1 , wherein a channel length of the first n-type transistor is the same as a channel length of the second n-type transistor. 11. A static electricity protection device comprising: a first p-type transistor; a first n-type transistor; a second p-type transistor; a second n-type transistor; a first wiring line supplying a first electric potential; a second wiring line supplying a data signal to a panel; and a third wiring line supplying a second electric potential higher than the first electric potential, wherein the first p-type transistor is disposed between the first wiring line and the second wiring line, one of a source and a drain of the first p-type transistor and a gate of the first p-type transistor are connected to the second wiring line, and the other one of the source and the drain of the first p-type transistor is connected to the first wiring line; the first n-type transistor is disposed between the first wiring line and the second wiring line, one of a source and a drain of the first n-type transistor and a gate of the first n-type transistor are connected to the first wiring line, and the other one of the source and the drain of the first n-type transistor is connected to the second wiring line; the second p-type transistor is disposed between the third wiring line and the second wiring line, one of a source and a drain of the second p-type transistor and a gate of the second p-type transistor are connected to the third wiring line, and the other one of the source and the drain of the second p-type transistor is connected to the second wiring line; and the second n-type transistor disposed between the third wiring line and the second wiring line, one of a source and a drain of the second n-type transistor and a gate of the second n-type transistor are connected to the second wiring line, and the other one of the source and the drain of the second n-type transistor is connected to the third wiring line. 12. An electronic device comprising the static electricity protection device according to claim 11 . 13. An electro-optic device comprising the static electricity protection device according to claim 11 . 14. An electronic device comprising the electro-optic device according to claim 13 . 15. A static electricity protection device comprising: a first p-type transistor; a first n-type transistor; a second p-type transistor; a second n-type transistor; a low electric potential wiring supplied with a first electric potential; a signal wiring supplied with a second electric potential higher than the first electric potential; and a high electric potential wiring supplied with a third electric potential higher than both the first electric potential and the second electric potential, wherein the first p-type transistor is disposed between the low electric potential wiring and the signal wiring, one of a source and a drain of the first p-type transistor and a gate of the first p-type transistor are connected to the signal wiring, and the other one of the source and the drain of the first p-type transistor is connected to the low electric potential wiring; the first n-type transistor is disposed between the low electric potential wiring and the signal wiring, one of a source and a drain of the first n-type transistor and a gate of the first n-type transistor are connected to the low electric potential wiring, and the other one of the source and the drain of the first n-type transistor is connected to the signal wiring; the second p-type transistor disposed between the high electric potential wiring and the signal wiring, one of a source and a drain of the second p-type transistor and a gate of the second p-type transistor are connected to the high electric potential wiring, and the other one of the source and the drain of the second p-type transistor is connected to the signal wiring; and the second n-type transistor disposed between the high electric potential wiring and the signal wiring, one of a source and a drain of the second n-type transistor and a gate of the second n-type transistor are connected to the signal wiring, and the other one of the source and the drain of the second n-type transistor is connected to the high electric potential wiring. 16. An electronic device comprising the static electricity protection device according to claim 15 . 17. An electro-optic device comprising the static electricity protection device according to claim 15 . 18. An electronic device comprising the electro-optic device according to claim 17 .
adapted for preventing breakage, peeling or short circuiting · CPC title
the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title
wherein the TFTs are in active matrices · CPC title
using FETs as protective elements · CPC title
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.