Integrated circuit on flexible substrate manufacturing process

Patent metadata

Field	Value
Publication number	US-11462575-B2
Application number	US-201916964513-A
Country	US
Kind code	B2
Filing date	Jan 30, 2019
Priority date	Jan 30, 2018
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.

First claim

The invention claimed is:

1. A process for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising:
providing a carrier for a flexible substrate;
depositing a flexible substrate of uniform thickness on said carrier;
patterning said uniform thickness flexible substrate to define a plurality of IC substrate areas spaced apart from one another by a plurality of IC connecting areas;
removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels prior to a step of forming an integrated circuit on at least one of the IC substrate units; and
removing a first portion of the thickness of the flexible substrate from a first portion of each of the IC connecting areas and removing a second portion of the thickness of the flexible substrate from a second, different portion of each of the IC connecting areas, wherein the first portion is of greater thickness than the second portion.

2. The process according to claim 1 , further comprising forming integrated circuits on each of the IC substrate units.

3. The process according to claim 1 , wherein each IC substrate unit comprises flexible substrate of uniform thickness.

4. The process according to claim 1 , further comprising removing the entire thickness of the flexible substrate from all of each of the IC connecting areas so as to form a plurality of substrate-free channels on the carrier between each of the IC substrate units on the carrier.

5. The process according to claim 1 , further comprising removing the entire thickness of the flexible substrate from a portion of each of the IC connecting areas so as to form a plurality of patterned channels on the carrier wherein at least one channel is formed between each of the IC substrate units.

6. The process according to claim 5 , comprising forming perforation lines between adjacent IC substrate units in the IC connecting areas by sequentially removing and leaving the entire thickness of the flexible substrate along each of the IC connecting areas so as to form a plurality of patterned channels on the carrier wherein at least one channel is formed between each of the IC substrate units.

7. The process according to claim 5 , comprising forming perforation lines between adjacent IC substrate units in the IC connecting areas by sequentially removing a first portion of the thickness of the flexible substrate from a first portion of each of the IC connecting areas and removing a second portion of the thickness of the flexible substrate from a second, different portion of each of the IC connecting areas, wherein the first portion is of greater thickness than the second portion, or comprising forming perforation lines between adjacent IC substrate units in the IC connecting areas by sequentially removing the entire thickness of the flexible substrate and a partial thickness of the flexible substrate along each of the IC connecting areas so as to form a plurality of patterned channels on the carrier wherein at least one channel is formed between each of the IC substrate units.

8. The process according to claim 1 , further comprising forming at least one structure in the IC connecting areas by removing the entire thickness of the flexible substrate from a portion of each of the IC connecting areas so as to form a channel having at least one structure of flexible substrate in the channel, the structure being spaced apart from the IC substrate units adjacent to the channel.

9. The process according to claim 1 , wherein the IC substrate units on the carrier are uniform in shape.

10. The process according to claim 1 , wherein at least one edge of at least one of the IC substrate units on the carrier comprises at least one indentation.

11. The process according to claim 1 , wherein the carrier is rigid.

12. The process according to claim 1 , wherein the carrier is flexible.

13. The process according to claim 1 , wherein at least a portion of the flexible substrate is removed from the IC connecting areas to form channels in a pattern at predetermined location(s) on the carrier.

14. The process according to claim 1 , wherein the flexible substrate is formed of a single layer, or wherein the flexible substrate comprises a layered structure comprising two polymer substrate layers spaced apart from one another by an interlayer.

15. The process according to claim 1 , wherein the flexible substrate material comprises a polymer or one or more of polyimide, polyethylene terephthalate (PET), parylene, benzocyclobutene, Cytop™, negative epoxy photoresist, hydrogen silsesquioxane (HSQ) and Polyaryletheretherketone (PEEK), or one or more of: a metal oxide, a metal phosphate, a metal sulphates, a metal sulphite, a metal nitride, a metal oxynitride, an inorganic insulator and a spinnable glass.

16. The process according to claim 1 , wherein an interface between the carrier and the flexible substrate is formed by direct adhesion of the flexible substrate to the carrier.

17. The process according to claim 1 , wherein an interface between the carrier and the flexible substrate comprises an interlayer.

18. The process according to claim 1 , comprising the step of singulating the IC substrate units by releasing each of them from the carrier following the completion of the IC formation process thereon.

Assignees

• Pragmatic Printing Ltd

Inventors

• Price Richard
• Cobb Brian
• Davies Neil

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

• H10W46/401

  for identification or tracking · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title