System and method for die crack detection in a CMOS bonded array

Patent metadata

Field	Value
Publication number	US-11450575-B2
Application number	US-202117181648-A
Country	US
Kind code	B2
Filing date	Feb 22, 2021
Priority date	Oct 5, 2020
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A system and method for die crack detection in a CMOS bonded array includes a capacitor that is formed in an edge seal, where one of the capacitor plates is in the edge seal portion of a first wafer, and the other capacitor plate is in the edge seal portion of a second wafer. A crack in the die can be detected by applying an alternating current waveform to a testing contact on the integrated circuit and monitoring for a shift in the alternating current waveform, as a crack would cause modulation in the capacitance.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first wafer comprising a plurality of memory dies; and
a second water comprising a plurality of control dies comprising control circuitry for the memory dies, wherein the first and second waters are bonded together at a bonding interface creating a plurality of bonded memory and control dies;
wherein each bonded memory and control die comprises:
a first edge seal portion on a memory-die-side of the bonding interface that comprises a first capacitor plate;
a second edge seal portion on a controller-die-side of the bonding interface that comprises a second capacitor plate, wherein the first and second capacitor plates are positioned on either side of the bonding interface to form a capacitor; and
a plurality of external testing contacts electrically coupled with one of the first and second capacitor plates to detect a discontinuity in the bonding interface between the memory die and the control die.

2. The integrated circuit of claim 1 , wherein the control circuitry comprises complementary metal-oxide-semiconductor (CMOS) circuitry.

3. The integrated circuit of claim 1 , wherein the plurality of external testing contacts are on the first wafer.

4. The integrated circuit of claim 1 , wherein the plurality of external testing contacts are on the second wafer.

5. The integrated circuit of claim 1 , wherein the first capacitor plate is formed by trench formation and metal fill in the first wafer.

6. The integrated circuit of claim 1 , wherein the second capacitor plate is formed by trench formation and metal fill in the second wafer.

7. A method for detecting a discontinuity in a bonding interface, the method comprising:
applying an alternating current waveform to a contact that is electrically coupled with a capacitor plate formed in an integrated circuit; and
detecting a bonding interface discontinuity by detecting a shift in the alternating current waveform;
wherein the integrated circuit comprises:
a first wafer comprising a plurality of memory dies; and
a second wafer comprising a plurality of control dies comprising control circuitry for the memory dies, wherein the first and second wafers are bonded together at a bonding interface creating a plurality of bonded memory and control dies;
wherein each bonded memory and control die comprises:
a first edge seal portion on a memory-die-side of the bonding interface that comprises a first capacitor plate;
a second edge seal portion on a controller-die-side of the bonding interface that comprises a second capacitor plate, wherein the first and second capacitor plates are positioned on either side of the bonding interface to form a capacitor; and
a plurality of external testing contacts electrically coupled with one of the first and second capacitor plates to detect a discontinuity in the bonding interface between the memory die and the control die.

8. The method of claim 7 , wherein the control circuitry comprises complementary metal-oxide-semiconductor (CMOS) circuitry.

9. The method of claim 7 , wherein the plurality of external testing contacts are on the first wafer.

10. The method of claim 7 , wherein the plurality of external testing contacts are on the second wafer.

11. The method of claim 7 , wherein the first and second capacitor plates are formed by trench formation and metal fill.

12. An integrated circuit comprising:
a first wafer comprising a plurality of memory dies; and
a second water comprising a plurality of control dies comprising control circuitry for the memory dies, wherein the first and second wafers are bonded together at a bonding interface creating a plurality of bonded memory and control dies;
wherein each bonded memory and control die comprises:
a first edge seal portion on a memory-die-side of the bonding interface that comprises a first capacitor plate;
a second edge seal portion on a controller-die-side of the bonding interface that comprises a second capacitor plate, wherein the first and second capacitor plates are positioned on either side of the bonding interface to form a capacitor; and
means for detecting a discontinuity in the bonding interface between the memory die and the control die.

13. The integrated circuit of claim 12 , wherein the means for detecting comprises a plurality of external testing contacts electrically coupled with one of the first and second capacitor plates.

14. The integrated circuit of claim 12 , wherein the first and second capacitor plates are formed by trench formation and metal fill.

15. The integrated circuit of claim 13 , wherein the plurality of external testing contacts are on the first wafer.

16. The integrated circuit of claim 13 , wherein the plurality of external testing contacts are on the second wafer.

17. The integrated circuit of claim 12 , wherein the memory dies comprise NAND dies and the control dies comprise complementary metal-oxide-semiconductor (CMOS) circuitry.

18. The integrated circuit of claim 1 , wherein the first and second capacitor plates are located in a gap that is formed in the first and second edge seal portions after the first and second wafers are bonded together.

19. The method of claim 7 , wherein the first and second capacitor plates are located in a gap that is formed in the first and second edge seal portions after the first and second wafers are bonded together.

20. The integrated circuit of claim 12 , Wherein the first and second capacitor plates are located in a gap that is formed in the first and second edge seal portions after the first and second wafers are bonded together.

Assignees

• Western Digital Tech Inc

Inventors

• Pachamuthu Jayavel
• Periyannan Kirubakaran
• Linnen Daniel

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• G01R31/312

  by capacitive methods · CPC title