Methods to selectively embed magnetic materials in substrate and corresponding structures

Patent metadata

Field	Value
Publication number	US-11450471-B2
Application number	US-201815938119-A
Country	US
Kind code	B2
Filing date	Mar 28, 2018
Priority date	Mar 28, 2018
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

First claim

What is claimed is:

1. An inductor, comprising
an inductor trace; and
a magnetic body surrounding the inductor trace, wherein the magnetic body comprises a first step surface and a second step surface, the first step surface and the second step surface on a same lateral side of the magnetic body.

2. The inductor of claim 1 , wherein the inductor is integrated into a package substrate.

3. The inductor of claim 2 , further comprising:
pillars embedded within the package substrate, wherein the magnetic body contacts surfaces of the pillars.

4. The inductor of claim 3 , further comprising:
a first conductive layer contacting a surface of each of the pillars, wherein the first step surface is substantially coplanar with a surface of the first conductive layer.

5. The inductor of claim 4 , wherein the first conductive layer is substantially the same thickness as the inductor trace.

6. The inductor of claim 3 , wherein the pillars have substantially vertical sidewalls.

7. The inductor of claim 3 , wherein a surface of the inductor trace is substantially coplanar with first surfaces of the pillars.

8. The inductor of claim 2 , wherein the package substrate is a coreless package substrate.

9. The inductor of claim 1 , wherein the inductor is a transmission line inductor, a spiral inductor, or a solenoid inductor.

10. An inductor comprising:
a barrier layer;
an inductor trace over a first surface of the barrier layer;
a first magnetic body over the inductor trace and the first surface of the barrier layer; and
a second magnetic body over a second surface of the barrier layer opposite the first surface, wherein a width of the second magnetic body is greater than a width of the first magnetic body, and wherein the second magnetic body is not in contact with first magnetic body.

11. The inductor of claim 10 , wherein sidewalls of the second magnetic body are substantially vertical.

12. The inductor of claim 11 , wherein sidewalls of the second magnetic body include a stepped surface.

13. The inductor of claim 11 , wherein sidewalls of the first magnetic body are tapered.

14. The inductor of claim 10 , wherein the barrier layer is less than approximately 5 μm.

15. The inductor of claim 10 , wherein the inductor is integrated into a package substrate.

16. The inductor of claim 15 , wherein pillars are formed into the package substrate, and wherein sidewalls of the second magnetic body contact the pillars.

17. The inductor of claim 15 , wherein the package substrate is a coreless substrate.

18. The inductor of claim 15 , wherein the package substrate includes a core.

19. The inductor of claim 10 , wherein the inductor is a transmission line inductor, a spiral inductor, or a solenoid inductor.

Assignees

• Intel Corp

Inventors

• Xu Cheng
• Lee Kyu-Oh
• Zhao Junnan
• Jain Rahul
• Park Ji Yong
• Vadlamani Sai
• Kim Seo Young

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H05K2201/10

  Details of components or other objects attached to or integrated in a printed circuit board · CPC title

• H01F27/022 Primary

  Encapsulation · CPC title