Multi-package system using configurable input/output interface circuits for single-ended intra-package communication and differential inter-package communication

Patent metadata

Field	Value
Publication number	US-11449453-B2
Application number	US-202117165898-A
Country	US
Kind code	B2
Filing date	Feb 2, 2021
Priority date	Apr 16, 2020
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A multi-package system includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first die and a second die. The second semiconductor package includes a third die. A first processing circuit of the first die communicates with a second processing circuit of the second die through a first configurable input/output (IO) interface circuit of the first die and a third configurable IO interface circuit of the second die that are configured to perform single-ended intra-package communication. The first processing circuit of the first die communicates with a third processing circuit of the third die through a second configurable IO interface circuit of the first die and a fourth configurable IO interface circuit of the third die that are configured to perform differential inter-package communication. The first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.

First claim

What is claimed is:

1. A multi-package system comprising:
a first semiconductor package, comprising:
a first die, comprising:
a first processing circuit, arranged to perform designated functions;
a first configurable input/output (TO) interface circuit; and
a second configurable IO interface circuit;

a second die, comprising:
a second processing circuit, arranged to perform designated functions; and
a third configurable IO interface circuit, coupled to the first configurable IO circuit via intra-package traces; and

a second semiconductor package, comprising:
a third die, comprising:
a third processing circuit, arranged to perform designated functions; and
a fourth configurable IO interface circuit, coupled to the second configurable IO interface circuit via inter-package traces;

wherein the first processing circuit communicates with the second processing circuit through the first configurable IO interface circuit and the third configurable IO interface circuit that are configured to perform single-ended intra-package communication; the first processing circuit communicates with the third processing circuit through the second configurable IO interface circuit and the fourth configurable IO interface circuit that are configured to perform differential inter-package communication; and the first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.

2. The multi-package system of claim 1 , wherein said same circuit design comprises:
a first channel circuit, comprising:
a first multiplexer, arranged to multiplex a first parallel data input obtained from the first processing circuit to generate a first serial data output; and
a first driving circuit, arranged to generate a first transmit (TX) bitstream according to the first serial data output; and

a second channel circuit, comprising:
a second multiplexer, arranged to multiplex a second parallel data input obtained from the first processing circuit to generate a second serial data output; and
a second driving circuit, arranged to generate a second TX bitstream according to the second serial data output;

wherein regarding the first configurable TO interface circuit, the first parallel data input and the second parallel data input obtained from the first processing circuit are single-ended data inputs, respectively; and
wherein regarding the second configurable TO interface circuit, the first parallel data input and the second parallel data input obtained from the first processing circuit form a differential data input.

3. The multi-package system of claim 2 , wherein regarding the first configurable TO interface circuit, no single-ended clock data input is received for transmission.

4. The multi-package system of claim 2 , wherein regarding the second configurable TO interface circuit, no differential clock data input is received for transmission.

5. The multi-package system of claim 2 , wherein regarding the first configurable TO interface circuit, one of the single-ended data inputs is a single-ended clock data input.

6. The multi-package system of claim 2 , wherein regarding the second configurable IO interface circuit, the differential data input is a differential clock data input.

7. The multi-package system of claim 1 , wherein said same circuit design comprises:
a multiplexer, arranged to multiplex a parallel data input obtained from the first processing circuit to generate a serial data output, wherein the parallel data input is a single-ended data input; and
a first driving circuit, arranged to generate a first transmit (TX) bitstream according to the serial data output, wherein the first driving circuit comprises an auxiliary processing circuit arranged to generate a second TX bitstream according to the serial data output, where the second TX bitstream is an inverse version of the first TX bitstream;
wherein regarding the first configurable IO interface circuit, the second TX bitstream is not output to any of the intra-package traces; and
wherein regarding the second configurable IO interface circuit, the first TX bitstream and the second TX bitstream that form a differential TX bitstream are output to at least a portion of the inter-package traces.

8. The multi-package system of claim 7 , wherein regarding the first configurable IO interface circuit, no single-ended clock data input is received for transmission.

9. The multi-package system of claim 7 , wherein regarding the second configurable IO interface circuit, no differential clock data input is received for transmission.

10. The multi-package system of claim 7 , wherein regarding the first configurable IO interface circuit, the parallel data input is a single-ended clock data input.

11. The multi-package system of claim 7 , wherein regarding the second configurable TO interface circuit, the parallel data input is a differential clock data input.

12. The multi-package system of claim 1 , wherein said same circuit design comprises:
a receive (RX) front-end circuit, comprising:
a comparator circuit, having a first input node, a second input node, and an output node, wherein a serial data input generated from the RX front-end circuit is derived from a comparator output at the output node;

wherein regarding the first configurable TO interface circuit, the first input node of the comparator is configured to receive a single-ended RX bitstream, and the second input node of the comparator is configured to receive a reference voltage; and
wherein regarding the second configurable TO interface circuit, the first input node of the comparator is configured to receive a first RX bitstream, and the second input node of the comparator is configured to receive a second RX bitstream, where the first RX bitstream and the second RX bitstream form a differential RX bitstream.

13. The multi-package system of claim 12 , wherein the reference voltage is an internal voltage of the first die.

14. The multi-package system of claim 12 , wherein the reference voltage is an external voltage supplied to the first die.

15. The multi-package system of claim 12 , wherein the RX front-end circuit further comprises an auxiliary processing circuit arranged to apply auxiliary processing to generation of the serial data input, one of the first configurable TO interface circuit and the second configurable TO interface circuit is configured to enable the auxiliary processing circuit, and another of the first configurable TO interface circuit and the second configurable TO interface circuit is configured to disable the auxiliary processing circuit.

16. The multi-package system of claim 12 , wherein said same circuit design further comprises:
a post-processing circuit, arranged to generate and output a parallel data input according to the serial data input, wherein the post-processing circuit comprises a clock and data recovery (CDR) circuit, and regarding the first configurable TO interface circuit, no single-ended clock data stream is received.

17. The multi-package system of claim 12 , wherein said same circuit design further comprises:
a post-processing circuit, arranged to generate and output a parallel data input according to the serial data input, wherein the post-processing circuit comprises a clock and data recovery (CDR) circuit, and regarding the second configurable TO interface circuit, no differential clock data stream is received.

18. The multi-package system of claim 12 , wherein regarding the first configurable TO interface circuit, the single-ended RX bitstream is a si

Assignees

• Mediatek Inc

Inventors

• Yeh Chun-Yuan
• Luo Yan-Bin
• Hsu Tse-Hsiang

Classifications

• H10W90/00

  Package configurations · CPC title

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• G06F13/20

  for access to input/output bus · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title

• H04B1/04 Primary

  Circuits · CPC title