Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces

Patent metadata

Field	Value
Publication number	US-9536863-B2
Application number	US-201113994919-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

First claim

What is claimed is:

1. An apparatus comprising:
a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits are impedance matched;
a first set of single-ended receiver circuits on a second die, wherein the first set of single-ended receiver circuits have no termination;
a first plurality of conductive lines between the first set of single-ended transmitter circuits and the first set of single-ended receiver circuits, wherein the lengths of the plurality of conductive lines are matched, wherein the first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the first plurality of conductive lines are disposed within a first package and wherein an equalizer circuit does not exist along corresponding channels between the first die and the second die that flow through the first set of single-ended transmitter circuits, the first plurality of conductive lines and the first set of single-ended receiver circuits;
a second set of single-ended transmitter circuits on the first die, wherein the second set of single-ended transmitter circuits are impedance matched, wherein data transmitted from the second set of single-ended transmitter circuits is transmitted according to a data bus inversion (DBI) scheme;
a second set of single-ended receiver circuits on a third die, wherein the second set of single-ended receiver circuits have termination; and
a second plurality of conductive lines between the second set of single-ended transmitter circuits and the second set of single-ended receiver circuits, wherein the lengths of the plurality of conductive lines are matched and the second set of single-ended receiver circuits and third die are disposed within a second package and wherein an equalizer circuit does not exist along corresponding channels between the first die and the third die that flow through the second set of single-ended transmitter circuits, the second plurality of conductive lines and the second set of single-ended receiver circuits.

2. The apparatus of claim 1 wherein the first package comprises a ball grid array (BGA) package.

3. The apparatus of claim 1 further comprising:
a third set of single-ended receiver circuits on the first die, wherein the third set of single-ended receiver circuits have no termination and no equalization;
a third set of single-ended transmitter circuits on the second die, wherein the third set of single-ended transmitter circuits are impedance matched and have no equalization; and
a third plurality of conductive lines between the second set of transmitter circuits and the second set of receiver circuits, wherein the lengths of the third set of plurality of conductive lines are matched.

4. The apparatus of claim 1 , wherein the first die comprises at least a processor core, the apparatus further comprising a touch screen interface coupled with the processor core.

5. The apparatus of claim 1 wherein a gap between the first die and the second die is less than 20 mm.

6. The apparatus of claim 5 wherein the gap is equal to or less than 1.5 mm.

7. A tablet computing device comprising:
a touch screen interface;
a first set of single-ended transmitter circuits on a first die, wherein the first-set of single ended transmitter circuits are impedance matched and have no equalization;
a first set of single-ended receiver circuits on a second die, wherein the first-set of single ended receiver circuits have no termination and no equalization;
a first plurality of conductive lines between the first set of single-ended transmitter circuits and the first set of single-ended receiver circuits, wherein the lengths of the plurality of conductive lines are matched, wherein the first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the first plurality of conductive lines are disposed within a first package and wherein an equalizer circuit does not exist along corresponding channels between the first die and the second die that flow through the first set of single-ended transmitter circuits, the first plurality of conductive lines and the first set of single-ended receiver circuits;
a second set of single-ended transmitter circuits on the first die, wherein the second set of single-ended transmitter circuits are impedance matched and have no equalization, wherein data transmitted from the second set of single-ended transmitter circuits is transmitted according to a data bus inversion (DBI) scheme;
a second set of single-ended receiver circuits on a third die, wherein the second set of single-ended receiver circuits have termination; and
a second plurality of conductive lines between the second set of single-ended transmitter circuits and the second set of single-ended receiver circuits, wherein the lengths of the plurality of conductive lines are matched and the second set of single-ended receiver circuits and third die are disposed within a second package and wherein an equalizer circuit does not exist along corresponding channels between the first die and the third die that flow through the second set of single-ended transmitter circuits, the second plurality of conductive lines and the second set of single-ended receiver circuits.

8. The tablet of claim 7 further comprising:
a third set of single-ended receiver circuits on the first die, wherein the third set of single-ended receiver circuits have no termination and no equalization;
a third set of single-ended transmitter circuits on the second die, wherein the third set of single-ended transmitter circuits are impedance matched and have no equalization; and
a third plurality of conductive lines between the second set of single-ended transmitter circuits and the second set of single-ended receiver circuits, wherein the lengths of the third plurality of conductive lines are matched.

9. The tablet of claim 7 further comprising an antenna for communication.

10. The tablet of claim 7 wherein a gap between the first die and the second die is less than 20 mm.

11. The tablet of claim 10 wherein the gap is equal to or less than 1.5 mm.

12. A system comprising:
an omnidirectional antenna;
a first set of single-ended transmitter circuits on a first die, wherein the first-set of single ended transmitter circuits are impedance matched and have no equalization;
a first set of single-ended receiver circuits on a second die, wherein the first-set of single ended receiver circuits have no termination and no equalization;
a first plurality of conductive lines between the first set of single-ended transmitter circuits and the first set of single-ended receiver circuits, wherein the lengths of the plurality of conductive lines are matched, wherein the first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the first plurality of conductive lines are disposed within a first package and wherein an equalizer circuit does not exist along corresponding channels between the first die and the second die that flow through the first set of single-ended transmitter circuits, the first plurality of conductive lines and the first set of single-ended receiver circuits;
a second set of single-ended transmitter circuits on the first die, wherein the second set of single-ended transmitter circuits are impedance matched and have no equalization, wherein data transmitted from the second set of single-ended transmitter circuits is transmitted according to a data bus inversion (DBI) scheme;
a second set of single-ended receiver circuits on a third d

Assignees

• Hinck Todd A
• Wu Zuoguo
• Martin Aaron
• Martwick Andrew W
• Halbert John B
• Intel Corp

Inventors

• Hinck Todd A
• Wu Zuoguo
• Martin Aaron
• Martwick Andrew W
• Halbert John B

Classifications

• H04B1/40

  Circuits · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title