Peak power determination for an integrated circuit device

US11449127B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11449127-B2
Application numberUS-201716642694-A
CountryUS
Kind codeB2
Filing dateSep 28, 2017
Priority dateSep 28, 2017
Publication dateSep 20, 2022
Grant dateSep 20, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

First claim

Opening claim text (preview).

The invention claimed is: 1. A circuit comprising peak power setting circuitry to set a peak power value for an integrated circuit device, the integrated circuit device having throttling circuitry to assert a power reducing feature of the integrated circuit device in response to a first throttling signal assertion, the peak power setting circuitry including: a power supply interface to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device; and processing circuitry to: determine a first approximate peak power for the integrated circuit device using the estimated peak power capacity of the power supply; determine a first peak power for the integrated circuit device by increasing the first approximate peak power for the integrated circuit device depending on an amount by which the integrated circuit device power is reduced in response to assertion of the throttling signal; and determine a second peak power for the integrated circuit device, the second peak power having a second approximate peak power different from the first approximate peak power, wherein the second peak power has a respective second throttling signal assertion to which the integrated circuit device has a corresponding power-reducing response, wherein the first peak power corresponds to a first power limit up to which the integrated circuit is permitted to sustain power for up to a first duration of time, and wherein the second peak power corresponds to a second power limit up to which the integrated circuit is permitted to sustain power for a second duration of time, wherein the second duration of time is different from the first duration of time. 2. The circuit of claim 1 , wherein the value to estimate the peak power capacity of the power supply comprises at least one of a peak battery power, a peak adapter power, and a dedicated power supply. 3. The circuit of claim 1 , wherein the first throttling signal assertion or the second throttling signal assertion indicates that at least one of: a threshold voltage, a threshold power, and a threshold current has been crossed. 4. The circuit of claim 1 , wherein the processing circuitry is to determine at least one further peak power for the integrated circuit device, the at least one further peak power having a further approximate peak power different from the first approximate peak power and the second peak power, and wherein the further peak power has a respective further throttling signal to which the integrated circuit device has a corresponding power-reducing response. 5. The circuit of claim 1 , wherein: the at least one further peak power includes a further peak power that corresponds to a third power limit up to which the integrated circuit is permitted to sustain power for a third duration of time, wherein the third duration of time is different from the first duration of time. 6. The circuit of claim 1 , the processing circuitry comprising: correction circuitry to correct the determined first peak power for the integrated circuit depending on a number of assertions of the first throttling signal in a given time period. 7. The circuit of claim 6 , wherein the correction to the determined first peak power comprises decreasing the determined first peak power relative to the increased first approximate peak power when the number of assertions of the first throttling signal in the given time period is higher than a threshold maximum number of throttling assertions. 8. The circuit of claim 6 , wherein the correction to the determined first peak power comprises increasing the determined first peak power relative to the increased first approximate peak power when the number of assertions of the first throttling signal in the given time period is lower than a threshold minimum number of throttling assertions. 9. The circuit of claim 6 , further comprising interrupt generating circuitry to send an interrupt to the processing circuitry responsive to at least one of: the number of first throttling signal assertions exceeding the threshold maximum number in the given time period; or the number of throttling signal assertions being less than the threshold minimum number in the given time period. 10. The circuit of claim 6 , wherein the correction circuitry is to determine the correction iteratively in response to at least one of: updates to the number of assertions of the first throttling signal and updates to the estimated peak power capacity of the power supply. 11. The circuit of claim 10 , wherein the correction circuitry is to implement a Proportional Integral Differential algorithm to perform the iterative correction. 12. The circuit of claim 1 , wherein the processing circuitry is responsive to an indication from a battery fuel gauge of a change in a peak power capability of a battery or of a battery state of charge, to update the first peak power determination using an updated value for the estimated peak power supply capacity. 13. The circuit of claim 1 , comprising threshold calculation circuitry to calculate the at least one of a threshold voltage, a threshold power, and a threshold current depending on the determined first peak power for the integrated circuit device. 14. The circuit of claim 13 , wherein the threshold calculation circuitry is arranged to calculate the at least one of the threshold voltage, threshold power, and threshold current using an estimate for an impedance of the battery supply based on a peak battery power. 15. The circuit of claim 14 , wherein the threshold calculation circuitry is to calculate the peak battery power based on the determined first peak power for the integrated circuit device. 16. The circuit of claim 14 , wherein the threshold calculation circuitry is to calculate the peak battery power based on at least one of: a peak power of an adapter of the power supply and the estimated power consumption of a rest of platform (ROP) excluding the integrated circuit device. 17. The circuit of claim 13 , wherein the threshold calculation circuitry is arranged to calculate the at least one of the threshold voltage, threshold power, and threshold current using a duration of time between the first throttling signal being asserted and the power reducing feature taking effect to reduce the power. 18. The circuit of claim 1 , wherein the power supply comprises a battery unit and wherein the power supply interface is to receive a value for a peak power capability of the battery unit and wherein the peak power capacity of the power supply is estimated using the peak power value of the battery unit. 19. The circuit of claim 1 , wherein the power supply interface is to receive an adapter peak power value and wherein the data processing circuitry is to estimate the peak power capacity of the power supply using the adapter peak power value. 20. The circuit of claim 1 , further comprising the integrated circuit. 21. The circuit of claim 1 , wherein peak power setting circuitry is included in an embedded controller. 22. At least one non-transitory machine-readable medium having instructions stored thereon that, when executed, cause processing hardware to: receive at least one value to estimate a peak power capacity of a power supply serving an integrated circuit device; determine a first approximate peak power for the integrated circuit device based on the estimated peak power capacity of the power supply; determine a first peak power for the integrated circuit device by increasing the first approx

Assignees

Inventors

Classifications

  • G06F1/3296Primary

    by lowering the supply or operating voltage · CPC title

  • G06F1/28Primary

    Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11449127B2 cover?
Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device i…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F1/3296. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 20 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).