System power management

Patent metadata

Field	Value
Publication number	US-2017293332-A1
Application number	US-201615093042-A
Country	US
Kind code	A1
Filing date	Apr 7, 2016
Priority date	Apr 7, 2016
Publication date	Oct 12, 2017
Grant date	—

Abstract

One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

First claim

What is claimed is:

1 . An apparatus comprising:
power control logic to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin); and a critical comparator to compare a system power consumption value (Psys) and the critical threshold, the critical comparator to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

2 . The apparatus of claim 1 , wherein the processor critical throttle signal is asserted within one microsecond of the system power consumption value increasing to greater than or equal to the critical threshold from less than the critical threshold.

3 . The apparatus of claim 1 , further comprising a first warning comparator and a first counter, the power control logic to set a first warning threshold and to provide the first warning threshold to the first warning comparator, the first warning threshold related to the critical threshold.

4 . The apparatus of claim 3 , wherein the first warning comparator is to compare the system power consumption value and the first warning threshold and the first counter is to at least one of initiate counting and/or continue counting if the system power consumption value is greater than or equal to the first warning threshold.

5 . The apparatus of claim 1 , wherein the power control logic is further to adjust the critical threshold in response to a change in the available input power value.

6 . The apparatus of claim 5 , wherein the power control logic is further to adjust at least one of the first warning threshold and/or a second warning threshold in response to a change in the critical threshold.

7 . The apparatus of claim 1 , wherein the power control logic is further to determine a target processor state based, at least in part, on a history.

8 . A method comprising:
determining, by power control logic, a critical threshold (TC) based, at least in part, on an available input power value (Pin); comparing, by a critical comparator, a system power consumption value (Psys) and the critical threshold; and asserting, by the critical comparator, a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

9 . The method of claim 8 , wherein the processor critical throttle signal is asserted within one microsecond of the system power consumption value increasing to greater than or equal to the critical threshold from less than the critical threshold.

10 . The method of claim 8 , further comprising setting, by the power control logic, a first warning threshold; and providing, by the power control logic, the first warning threshold to a first warning comparator, the first warning threshold related to the critical threshold.

11 . The method of claim 10 , further comprising comparing, by the first warning comparator, a system power consumption value and the first warning threshold; and at least one of initiating and/or continuing, by the first counter, counting, if the system power consumption value is greater than or equal to the first warning threshold.

12 . The method of claim 8 , further comprising adjusting, by the power control logic, the critical threshold in response to a change in the available input power value.

13 . The method of claim 12 , further comprising adjusting, by the power control logic, at least one of a first warning threshold and/or a second warning threshold in response to a change in the critical threshold.

14 . The method of claim 8 , further comprising determining, by the power control logic, the target processor state based, at least in part, on a history.

15 . A device comprising:
a processor; a communication interface; a peripheral device; and a power control module comprising:
power control logic to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin); and
a critical comparator to compare a system power consumption value (Psys) and the critical threshold,
the critical comparator to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

16 . The device of claim 15 , wherein the processor critical throttle signal is asserted within one microsecond of the system power consumption value increasing to greater than or equal to the critical threshold from less than the critical threshold.

17 . The device of claim 15 , wherein the power control module further comprises a first warning comparator and a first counter, the power control logic to set a first warning threshold and to provide the first warning threshold to the first warning comparator, the first warning threshold related to the critical threshold.

18 . The device of claim 17 , wherein the first warning comparator is to compare the system power consumption value and the first warning threshold and the first counter is to at least one of initiate counting and/or continue counting if the system power consumption value is greater than or equal to the first warning threshold.

19 . The device of claim 15 , wherein the power control logic is further to adjust the critical threshold in response to a change in the available input power value.

20 . The device of claim 19 , wherein the power control logic is further to adjust at least one of the first warning threshold and/or a second warning threshold in response to a change in the critical threshold.

21 . The device of claim 15 , wherein the power control logic is further to determine a target processor state based, at least in part, on a history.

22 . The device of claim 15 , further comprising a battery, the available input power value related to an available capacity of the battery.

23 . The device of claim 15 , wherein the system power consumption value is related to operation of one or more of the processor, communication interface and/or the peripheral device.

Assignees

• Intel Corp

Inventors

• Rotem Efraim
• Schiff Tod F
• Rajwan Doron
• Jull Jeffrey M
• Hermerding Ii James G
• Rosenzweig Nir
• Toledano Maytal
• Uan-Zo-Li Alexander B

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3212

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

• G08B25/08

  using communication transmission lines {(G08B13/19658, G08B21/0286, G08B25/016 take precedence)} · CPC title

• G08B21/182

  Level alarms, e.g. alarms responsive to variables exceeding a threshold · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title