Method and Apparatus for System Control of a Central Processing Unit (CPU) Maximum Power Detector

Patent metadata

Field	Value
Publication number	US-2016231802-A1
Application number	US-201514619727-A
Country	US
Kind code	A1
Filing date	Feb 11, 2015
Priority date	Feb 11, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A method and apparatus for system control of a central processing unit (CPU) maximum power detector are provided. in accordance with at least one embodiment, a decision is made as to whether a response of a maximum power detector of the CPU is to be altered. When the response is to be altered, a modified input level is provided to the maximum power detector to alter the response. As an example, the modified input level can prevent the maximum power detector from triggering a power throttling function. When the response is not to be altered, an existing input level for the maximum power detector is maintained. In accordance with at least one embodiment, an apparatus or information handling system can comprise a voltage regulator (VR), a current sensor, a CPU comprising a maximum power detector, and a digital to analog converter (DAC).

First claim

What is claimed is:

1 . Apparatus comprising:
a voltage regulator (VR); a current sensor coupled to the VR; a central processing unit (CPU) comprising a maximum power detector, the CPU coupled to the current sensor; and a digital to analog converter (DAC) coupled to the current sensor, the DAC for providing an output to influence operation of the maximum power detector.

2 . The apparatus of claim 1 further comprising:
a baseboard management controller (BMC) coupled to the DAC, the BMC configured to control the DAC.

3 . The apparatus of claim 2 wherein the BMC is configured to control the DAC to override a function of the maximum power detector.

4 . The apparatus of claim 3 wherein the BMC is configured to control the DAC to override a power throttle trigger function of the maximum power detector.

5 . The apparatus of claim 1 wherein the current sensor comprises a sense resistor between an output of the DAC and an input of the CPU.

6 . The apparatus of claim 1 wherein the current sensor comprises a resistor having a first end coupled to the VR and a second end coupled to the CPU and to an output of the DAC.

7 . The apparatus of claim 1 further comprising:
a power supply unit (PSU) coupled to the VR and to the DAC, the PSU configured to provide power to the VR.

8 . An information handling system comprising:
a voltage regulator (VR); a current sensor coupled to the VR; a central processing unit (CPU) comprising a maximum power detector, the CPU coupled to the current sensor; and a digital to analog converter (DAC) coupled to the current sensor, the DAC configured to provide an output to influence operation of the maximum power detector.

9 . The information handling system of claim 8 further comprising:
a baseboard management controller (BMC) coupled to the DAC, the BMC configured to control the DAC.

10 . The information handling system of claim 9 wherein the BMC is configured to control the DAC to override a function of the maximum power detector.

11 . The information handling system of claim 10 wherein the BMC is configured to control he DAC to override a power throttle trigger function of the maximum power detector.

12 . The information handling system of claim 8 wherein the current sensor comprises a sense resistor between an output of the DAC and an input of the CPU.

13 . The information handling system of claim 8 wherein the current sensor comprises a resistor having a first end coupled to the VR and a second end coupled to the CPU and to an output of the DAC.

14 . The information handling system of claim 8 further comprising:
a power supply unit (PSU) coupled to the VR and to the DAC, the PSU configured to provide power to the VR.

15 . A method comprising:
determining if a response of a maximum power detector of a central processing unit is to be altered; when the response of the maximum power detector is to be altered, providing a modified input level to the maximum power detector to alter the response, wherein the modified input level usurps control over the maximum power detector with respect to triggering a power throttling function; and when the response of the maximum power detector is not to be altered, maintaining an existing voltage for the maximum power detector.

16 . The method of claim 15 further comprising:
determining if the modified input level is low enough to disable he power throttling function;
when the modified input level is not low enough to disable the power throttling function, operating the maximum power detector in a modified manner, wherein the providing the modified input level to the maximum power detector to alter the response comprises:
preventing the maximum power detector from triggering a power throttling function.

17 . The method of claim 15 further comprising:
measuring power usage; and
comparing power usage to a power supply unit (PSU) capability.

18 . The method of claim 17 further comprising:
obtaining information representative of the PSU capability.

19 . The method of claim 15 further comprising:
controlling a throttle trigger to trigger power throttling when indicated.

20 . The method of claim 16 further comprising:
running a system based on a determined power configuration, wherein the determined power configuration is a result of the determining if a response of a maximum power detector of a central processing unit is to be altered and the determining if the modified input level is low enough to disable the power throttling function.

Assignees

• Dell Products Lp

Inventors

• Jenne John E
• Dube Shawn J
• Farkas Sandor

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3212

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

• G06F1/263

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F1/30

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title