Array substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11448932-B2
Application number	US-201916476292-A
Country	US
Kind code	B2
Filing date	Apr 16, 2019
Priority date	Dec 29, 2018
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

An array substrate and a manufacturing method thereof in the embodiment of the present invention can complete the process of the array substrate with the touch function by using six photolithography processes, thereby simplifying the production process, saving cost, and shortening the production cycle.

First claim

What is claimed is:

1. A manufacturing method of an array substrate, comprising:
depositing a buffer layer and a source-drain metal layer on a substrate in sequence, performing a first photolithography process to form a source electrode, a drain electrode, and a touch line;
depositing a polysilicon layer, performing a second photolithography process to form a conductive channel, the conductive channel being disposed between the source electrode and the drain electrode, and contacting with the source electrode and the drain electrode;
depositing a gate insulating layer and a pixel electrode layer in sequence, performing a third photolithography process to form a pixel electrode, forming a first via hole in the gate insulating layer above the touch line, and forming a second via hole in the gate insulating layer above the drain electrode;
depositing a gate metal layer, performing a fourth photolithography process to form a gate electrode, a first connection electrode, and a second connection electrode, wherein the first connection electrode is connected to the touch line through the first via hole, the second connection electrode is connected to the drain electrode through the second via hole, and forming a lightly doped area and a heavily doped area in the conductive channel;
depositing a flat layer, performing a fifth photolithography process to form a third via hole in the flat layer above the first connection electrode; and
depositing a common electrode layer, performing a sixth photolithography process to form a touch electrode and a common electrode, wherein the touch electrode is connected to the first connection electrode through the third via hole;
wherein the step of depositing the buffer layer and the source-drain metal layer on the substrate in sequence, performing the first photolithography process to form the source electrode, the drain electrode, and the touch line includes:
depositing the buffer layer, the source-drain metal layer and the first photoresist layer on the substrate in sequence, exposing and developing the first photoresist layer by using a first mask to form a first photoresist pattern;
etching the source-drain metal layer with the first photoresist pattern as a mask to form the source electrode, the drain electrode, and the touch line, and removing the first photoresist pattern;
the step of depositing the polysilicon layer, performing the second photolithography process to form the conductive channel includes:
depositing an amorphous silicon layer, and performing laser annealing on the amorphous silicon layer to form the polysilicon layer;
depositing a second photoresist layer on the polysilicon layer, exposing and developing the second photoresist layer using a second mask to form a second photoresist pattern; and
etching the polysilicon layer by using the second photoresist pattern as a mask to form the conductive channel, and removing the second photoresist pattern.

2. The manufacturing method of the array substrate as claimed in claim 1 , wherein the step of depositing the gate insulating layer and the pixel electrode layer in sequence, performing the third photolithography process to form the pixel electrode, forming the first via hole in the gate insulating layer above the touch line, and forming the second via hole in the gate insulating layer above the drain electrode includes:
depositing the gate insulating layer, the pixel electrode layer and the third photoresist layer in sequence, exposing and developing the third photoresist layer by using a third mask to form a third photoresist pattern;
etching the pixel electrode layer and the gate insulating layer with the third photoresist pattern as a mask to form the first via hole in the gate insulating layer above the touch line, and to form the second via hole in the gate insulating layer above the drain electrode;
performing an ion bombardment on the third photoresist pattern with oxygen to form a fourth photoresist pattern; and
etching the pixel electrode layer with the fourth photoresist pattern as a mask to form the pixel electrode, and removing the fourth photoresist pattern.

3. The manufacturing method of the array substrate as claimed in claim 2 , wherein the step of etching the pixel electrode layer and the gate insulating layer with the third photoresist pattern as a mask to form the first via hole in the gate insulating layer above the touch line, and to form the second via hole in the gate insulating layer above the drain electrode includes:
performing a wet etching process, etching the pixel electrode layer with the third photoresist pattern as a mask to remove the pixel electrode layer above the touch line, and removing the pixel electrode layer on the drain electrode; and
performing a dry etching process, etching the gate insulating layer with the third photoresist pattern as a mask to remove the gate insulating layer above the touch line, and removing the gate insulating layer on the drain electrode.

4. The manufacturing method of the array substrate as claimed in claim 2 , wherein the third mask is a halftone mask.

5. The manufacturing method of the array substrate as claimed in claim 1 , wherein the step of depositing the gate metal layer, performing the fourth photolithography process to form the gate electrode, the first connection electrode, and the second connection electrode, wherein the first connection electrode is connected to the touch line through the first via hole, the second connection electrode is connected to the drain electrode through the second via hole, and forms the lightly doped area and the heavily doped area in the conductive channel includes:
depositing the gate metal layer and the fourth photoresist layer in sequence, exposing and developing the fourth photoresist layer by a fourth mask to form a fifth photoresist pattern;
etching the gate metal layer with the fifth photoresist pattern as a mask to form the gate electrode, the first connection electrode, and the second connection electrode;
performing a first ion implantation process on the conductive channel to form the heavily doped area of the conductive channel;
performing an ion bombardment to the fifth photoresist pattern and the gate electrode with the chlorine and the oxygen to form a sixth photoresist pattern, and etching away a portion of the gate electrode;
performing a second ion implantation process on the conductive channel to form the lightly doped area of the conductive channel; and
removing the sixth photoresist pattern.

6. The manufacturing method of the array substrate as claimed in claim 1 , wherein the step of depositing the flat layer, performing the fifth photolithography process to form the third via hole in the flat layer above the first connection electrode includes:
depositing the flat layer and the fifth photoresist layer in sequence, exposing and developing the fifth photoresist layer by a fifth mask to form a seventh photoresist pattern;
etching the flat layer with the seventh photoresist pattern as a mask to form the third via hole in the flat layer above the first connection electrode; and
removing the seventh photoresist pattern.

7. The manufacturing method of the array substrate as claimed in claim 1 , wherein the step of depositing the common electrode layer, performing the sixth photolithography process to form the touch electrode and the common electrode, wherein the touch electrode is connected to the first connection electrode through the third via hole includes:
depositing the common electrode layer and the sixth photoresist layer in sequence, exposing and developing the sixth photoresist layer by a sixth mask to form an eighth photoresist pattern;
etching the common electrode layer with the eighth photoresist pattern as a mask to fo

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Yan Yuan
• Song Jiyue

Classifications

• H10P95/906

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• H10P50/263

  of silicon-containing layers · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• G02F2201/123

  pixel · CPC title