Spacerless source contact layer replacement process and three-dimensional memory device formed by the process

Patent metadata

Field	Value
Publication number	US-11444101-B2
Application number	US-202017038870-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Jun 30, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A lower source-level dielectric etch-stop layer, a source-level sacrificial layer, and an upper source-level dielectric etch-stop layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory stack structures are formed through the alternating stack. Backside openings are formed through the alternating stack and into the in-process source-level material layers such that tapered surfaces are formed through the upper source-level dielectric etch-stop layer. A source cavity is formed by removing the source-level sacrificial layer, and a continuous source contact layer is formed in the source cavity and in peripheral portions of the backside openings. Portions of the continuous source contact layer overlying the tapered surfaces are removed by performing an isotropic etch process. Remaining portions of the continuous source contact layer comprise a source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
source-level material layers located over a substrate and comprising, from bottom to top, a lower source-level dielectric etch-stop layer, a source contact layer, and an upper source-level dielectric etch-stop layer;
alternating stacks of insulating layers and electrically conductive layers located over the source-level material layers;
backside trenches laterally extending along a first horizontal direction and vertically extending between the alternating stacks and through the upper source-level dielectric etch-stop layer, wherein segments of sidewalls of the backside trenches located on the upper source-level dielectric etch-stop layer are tapered at a first taper angle with respect to a vertical direction;
memory openings vertically extending through the alternating stacks; and
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, wherein the source contact layer laterally surrounds and contacts a bottom end portion of each of the vertical semiconductor channels;
wherein:
a bottom surface of the upper source-level dielectric etch-stop layer and a top surface of the lower source-level dielectric etch-stop layer have elongated openings that laterally extend along the first horizontal direction; and
each elongated opening through the top surface of the lower source-level dielectric etch-stop layer is vertically coincident with or is laterally offset inward from a respective elongated opening through the bottom surface of the upper source-level dielectric etch-stop layer in a plan view.

2. The three-dimensional memory device of claim 1 , wherein segments of sidewalls of the backside trenches located on the alternating stacks are vertical or have a taper angle that is less than the first taper angle.

3. The three-dimensional memory device of claim 1 , wherein the source contact layer comprises:
planar portions located above a horizontal plane including a top surface of the lower source-level dielectric etch-stop layer; and
rail portions that protrude downward below the horizontal plane including the top surface of the lower source-level dielectric etch-stop layer.

4. The three-dimensional memory device of claim 3 , wherein each of the rail portions of the source contact layer underlies a respective one of the backside trenches, and is located entirely within an area defined by a periphery of the respective one of the backside trenches located within a horizontal plane including bottommost surfaces of the alternating stack.

5. The three-dimensional memory device of claim 4 , wherein each of the rail portions of the source contact layer comprises an upper periphery that is located within the horizontal plane including the top surface of the lower source-level dielectric etch-stop layer and is laterally offset inward from the periphery of the respective one of the backside trenches by a lateral offset distance.

6. The three-dimensional memory device of claim 3 , wherein sidewalls of the rail portions of the source contact layer have a second taper angle that is within a range from 70% to 130% of the first taper angle.

7. The three-dimensional memory device of claim 1 , wherein the lower source-level dielectric etch-stop layer and the upper source-level dielectric etch-stop layer comprise carbon at an atomic concentration in a range from 2% to 30%.

8. The three-dimensional memory device of claim 1 , wherein each of the lower source-level dielectric etch-stop layer and the upper source-level dielectric etch-stop layer comprises silicon oxide carbide.

9. The three-dimensional memory device of claim 1 , wherein an entirety of the source contact layer is a unitary structure that continuously extends underneath the alternating stacks and has a homogeneous material composition throughout.

10. The three-dimensional memory device of claim 1 , wherein:
the vertical semiconductor channels comprise a first doped semiconductor material having a doping of a first conductivity type;
the source contact layer comprises a second doped semiconductor material having a doping of a second conductivity type that is the opposite of the first conductivity type;
the memory films comprise outer sidewalls that contact the upper source-level dielectric etch-stop layer; and
the three-dimensional memory device comprises dielectric cap structures embedded in the lower source-level dielectric etch-stop layer, contacting a bottom end of a respective one of the vertical semiconductor channels, and comprising a stack of dielectric materials having a same set of dielectric materials as each of the memory films.

11. A method of forming a three-dimensional memory device, comprising:
forming in-process source-level material layers comprising, from bottom to top, a lower source-level dielectric etch-stop layer, a source-level sacrificial layer, and an upper source-level dielectric etch-stop layer over a substrate;
forming an alternating stack of insulating layers and sacrificial material layers over the in-process source-level material layers;
forming memory openings through the alternating stack and into the in-process source-level material layers;
forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective memory film;
forming backside openings through the alternating stack and into the in-process source-level material layers;
forming a source cavity by removing the source-level sacrificial layer selective to materials of the alternating stack, the upper source-level dielectric etch-stop layer, and the lower source-level dielectric etch-stop layer through the backside openings without sidewall spacers being located on the alternating stack in the backside openings;
forming a continuous source contact layer in the source cavity and in peripheral portions of the backside openings;
removing portions of the continuous source contact layer overlying the first tapered surfaces by performing an isotropic etch process, wherein remaining portions of the continuous source contact layer comprise a source contact layer; and
replacing the sacrificial material layers with electrically conductive layers through the backside openings.

12. The method of claim 11 , wherein:
the backside openings comprise backside trenches;
the backside trenches are formed by performing an anisotropic etch process employing an etchant gas; and
each of the upper source-level dielectric etch-stop layer and the lower source-level dielectric etch-stop layer has a higher etch resistance to the etchant gas than materials of the alternating stack, such that first tapered surfaces having a first taper angle are formed through the upper source-level dielectric etch-stop layer and second tapered surfaces having a second taper angle are formed through the lower source-level dielectric etch-stop layer.

13. The method of claim 12 , wherein the lower source-level dielectric etch-stop layer and the upper source-level dielectric etch-stop layer comprise carbon at an atomic concentration in a range from 2% to 30%.

14. The method of claim 13 , wherein each of the lower source-level dielectric etch-stop layer and the upper source-level dielectric etch-stop layer comprise silicon oxide carbide.

15. The method of claim 12 , further comprising isotropically etching physically exposed portions of the memory films after formation of the source cavity, wherein:
cylindrical sidewalls of the vertical semicon

Assignees

• Sandisk Technologies Llc

Inventors

• Sato Jo
• Funayama Kota
• Hinoue Tatsuya

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic