Integrated nanofluidic arrays for high capacity colloid separation
US-9700891-B2 · Jul 11, 2017 · US
Microfluidic chips with one or more vias filled with sacrificial plugs
US11440002B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11440002-B2 |
| Application number | US-201816168292-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 23, 2018 |
| Priority date | Oct 23, 2018 |
| Publication date | Sep 13, 2022 |
| Grant date | Sep 13, 2022 |
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- Title
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Abstract
Official abstract text for this publication.
Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus, comprising: a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer, wherein the plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer; a plurality of sacrificial plugs that respectively fill the plurality of vias, wherein the plurality of sacrificial plugs comprise a sacrificial material and are not integrally connected to each other by the sacrificial material, and wherein the plurality of sacrificial plugs block fluid communication through the plurality of vias; and a microfluidic element on the surface of the silicon device layer and adjacent to the plurality of vias, wherein the microfluidic element comprises a nanoscale condenser array. 2. The apparatus of claim 1 , wherein the plurality of sacrificial plugs are extractable by a dry debonding process. 3. The apparatus of claim 1 , wherein the sacrificial material comprises a polyimide adhesive. 4. The apparatus of claim 1 , wherein the respective removable sacrificial plugs are removable by an oxygen plasma debonding process. 5. The apparatus of claim 1 , wherein the plurality of vias have respective diameters greater than or equal to 5 μm and less than or equal to 0.5 mm. 6. The apparatus of claim 1 , wherein the sacrificial material comprises a temporary wafer bonding material. 7. The apparatus of claim 1 , wherein the sacrificial material comprises a B-staged bisbenzocyclobutene monomer derived resin. 8. An apparatus, comprising: a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer, wherein the plurality of vias comprise respective removable sacrificial plugs that fill the plurality of vias, wherein the respective removable sacrificial plugs comprise a sacrificial material and are not integrally connected to each other by the sacrificial material, and wherein the respective removable sacrificial plugs block fluid communication through the plurality of vias, wherein the plurality of vias have respective diameters greater than or equal to 5 μm and less than or equal to 0.5 mm; and a nanoscale condenser array on the surface of the silicon device layer and adjacent to the plurality of vias. 9. The apparatus of claim 8 , wherein the plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. 10. The apparatus of claim 8 , wherein the respective removable sacrificial plugs are removable by a dry debonding process. 11. The apparatus of claim 8 , wherein the respective removable sacrificial plugs are removable by an oxygen plasma debonding process. 12. The apparatus of claim 8 , wherein the sacrificial material comprises a polyimide adhesive. 13. The apparatus of claim 8 , wherein the sacrificial material comprises a temporary wafer bonding material. 14. The apparatus of claim 8 , wherein the sacrificial material comprises a B-staged bisbenzocyclobutene monomer derived resin. 15. An apparatus, comprising: a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer, wherein the plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer; a plurality of sacrificial plugs that respectively fill the plurality of vias, wherein the plurality of sacrificial plugs comprise a sacrificial material and are not integrally connected to each other by the sacrificial material, and wherein the plurality of sacrificial plugs block fluid communication through the plurality of vias; and a microfluidic element on the surface of the silicon device layer and adjacent to the plurality of vias, wherein the microfluidic element comprises a deterministic lateral displacement array. 16. The apparatus of claim 15 , wherein the plurality of sacrificial plugs are extractable by a dry debonding process. 17. The apparatus of claim 15 , wherein the sacrificial material comprises a polyimide adhesive. 18. The apparatus of claim 15 , wherein the sacrificial material comprises a temporary wafer bonding material. 19. The apparatus of claim 15 , wherein the sacrificial material comprises a B-staged bisbenzocyclobutene monomer derived resin. 20. The apparatus of claim 15 , wherein the respective removable sacrificial plugs are removable by an oxygen plasma debonding process.
Assignees
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Classifications
Channels · CPC title
- B01L3/502707Primary
characterised by the manufacture of the container or its components · CPC title
rectangular shaped · CPC title
having a very large number of wells, microfabricated wells · CPC title
Three dimensional network · CPC title
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Frequently asked questions
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- What does patent US11440002B2 cover?
- Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comp…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification B01L3/502707. Mapped technology areas include Operations & Transport.
- When was this patent published?
- Publication date Tue Sep 13 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).