Wafer level packaging techniques

Patent metadata

Field	Value
Publication number	US-9269679-B2
Application number	US-201314072141-A
Country	US
Kind code	B2
Filing date	Nov 5, 2013
Priority date	Nov 5, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

First claim

What is claimed is:

1. A packaged integrated circuit (IC) structure comprising:
a first substrate comprising a CMOS device and a CMOS bond ring,
a second substrate laterally extending across an outer sidewall of the first substrate, the second substrate comprising a MEMS device and a MEMS bond ring, the MEMS bond ring surrounding a periphery of the MEMS device and being bonded to the CMOS bond ring; and
a protection layer covering outer sidewalls of the MEMS bond ring and outer sidewalls of the CMOS bond ring, and further covering the outer sidewall of the first substrate and not covering an outer sidewall of the second substrate;
wherein the protection layer has an upper surface that is aligned with an upper surface of the first substrate.

2. The packaged IC structure of claim 1 , wherein the outer sidewall of the second substrate meets an outer sidewall of the protection layer to define a planar surface at which the packaged IC structure was diced.

3. The packaged IC structure of claim 1 , wherein the outer sidewalls of the MEMS bond ring and CMOS bond ring are laterally recessed relative to the outer sidewall of the first substrate.

4. The packaged IC structure of claim 1 , wherein the MEMS bond ring and CMOS bond ring meet to form an enclosed cavity which is in fluid communication with the MEMS device and which is hermetically sealed from an ambient environment surrounding the packaged IC structure.

5. The packaged IC structure of claim 1 , further comprising an electrical connection structure connecting the CMOS device to a top side of the first substrate, the top side opposing a bottom side of the first substrate on which the CMOS bond ring is arranged.

6. A wafer level package structure, comprising:
a first substrate;
a second substrate comprising a plurality of MEMS devices;
an array of bond ring structures arranged between the first and second substrates, wherein interior sidewalls of a bond ring structure define a cavity between a first surface of the first substrate and a first surface of the second substrate; and
a test line arranged on or proximate to the first surface of the second substrate, wherein the test line is arranged in a scribe line area between opposing outer sidewalls of neighboring bond ring structures and is electrically coupled to a MEMS device on the second substrate.

7. The wafer level package structure of claim 6 , further comprising:
a deep trench in the first substrate, wherein the deep trench is aligned in the scribe line area over the test line.

8. The wafer level package structure of claim 7 , wherein the deep trench is filled with a protection material including photo resist, polyimide, epoxy, spin-on-glass material, or molding material.

9. The wafer level package structure of claim 6 , wherein the cavity is filled with an inert gas.

10. The wafer level package structure of claim 6 , wherein the first substrate comprises a plurality of CMOS devices.

11. The wafer level package structure of claim 10 , wherein a bond ring structure comprises a CMOS bond ring on the first substrate and a MEMS bond ring on the second substrate.

12. The wafer level package structure of claim 11 , wherein the MEMS bond ring is comprised of a material selected from a group consisting of indium, gold, tin, copper, aluminum, germanium and combinations thereof.

13. The wafer level package structure of claim 11 , wherein the CMOS bond ring is comprised of a material selected from a group consisting of indium, gold, tin, copper, aluminum, germanium and combinations thereof.

14. The wafer level package structure of claim 11 , wherein a bond between the MEMS bond ring and CMOS bond ring is a eutectic metal bond or a eutectic Al/Ge bond.

15. The wafer level package structure of claim 6 , further comprising:
a through silicon via, a ball grid array, or a re-distribution layer arranged on a top side of the first substrate to provide electrical connection from the top side of the first substrate.

16. A packaged integrated circuit (IC) structure comprising:
a first bond ring arranged on a first substrate and laterally set back from an outer sidewall of the first substrate;
a second bond ring arranged on a second substrate and bonded to the first bond ring to enclose a hermetic cavity therebetween, wherein the second bond ring is laterally set back from an outer sidewall of the second substrate;
a protection layer abutting outer sidewalls of the first and second bond rings, and not abutting the outer sidewall of the second substrate; and
a through silicon via extending from a to side of the first substrate to a position within the first substrate that vertically overlies the cavity.

17. The packaged IC structure of claim 16 , wherein the outer sidewalls of the first and second substrates are vertically aligned with an outer sidewall of the protection layer.

18. The packaged IC structure of claim 16 , wherein the second substrate has a lateral dimension that is greater than that of the first substrate.

19. The packaged IC structure of claim 16 , wherein the protection layer has an upper surface that is co-planar with a top side of the first substrate.

20. The packaged IC structure of claim 16 , wherein the first substrate is a CMOS substrate comprising a CMOS device and the second substrate is a MEMS substrate comprising a MEMS device, wherein the through silicon via is coupled to the CMOS device of the CMOS substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Teng Yi-Chuan
• Peng Jung-Huei
• Tsai Shang-Ying
• Hung Li-Min
• Huang Yao-Te
• Cho Chin-Yi

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W72/0198 Primary

  batch processes · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W72/936

  Multiple bond pads having different shapes · CPC title