Analog to digital converter with VCO-based and pipelined quantizers

Patent metadata

Field	Value
Publication number	US-11438007-B2
Application number	US-202117181381-A
Country	US
Kind code	B2
Filing date	Feb 22, 2021
Priority date	Mar 31, 2020
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

First claim

What is claimed is:

1. An analog-to-digital conversion method, comprising:
receiving an analog input signal;
converting the analog input signal to a first digital signal in a frequency domain, the first digital signal including an error component;
converting the first digital signal to an analog output signal;
summing the analog output signal, the analog input signal, and a filtered version of the analog input signal to extract the error component;
converting a negative of the error component to a digital error signal; and
summing the first digital signal and the digital error signal; and
outputting a digital output signal corresponding to the analog input signal.

2. The method of claim 1 , further comprising:
applying a first gain factor to the negative of the error component; and
applying an inverse of the first gain factor to the digital error signal.

3. The method of claim 2 , wherein the first gain factor is applied by a transimpedance amplifier.

4. The method of claim 1 , further comprising delaying the first digital signal before summing the first digital signal and the digital error signal.

5. The method of claim 1 , wherein the first digital signal includes a first number of bits and the digital error signal includes a second number of bits greater than the first number.

6. The method of claim 1 , wherein the analog input signal is converted to the first digital signal by a Delta-Sigma analog to digital converter (ADC).

7. The method of claim 6 , wherein converting the analog input signal to the first digital signal in the frequency domain includes applying the analog input signal to a voltage controlled oscillator (VCO).

8. The method of claim 1 , wherein the error component includes a quantization error and a harmonic distortion.

9. An analog-to-digital converter (“ADC”), comprising:
an input terminal configured to receive an analog input signal;
a VCO-based Delta-Sigma ADC circuit coupled to the input terminal and configured to output a first digital signal in a frequency domain based on the analog input signal;
a first digital-to-analog converter (DAC) configured to convert the first digital signal to an analog output signal;
a first summation circuit configured to receive the analog output signal and the analog input signal;
a pipelined ADC circuit configured to convert an output of the first summation circuit to a second digital signal;
a second summation circuit configured to receive the first digital signal and the second digital signal, and output a digital output signal corresponding to the analog input signal at an output terminal.

10. The ADC of claim 9 , further comprising a digital filter coupled to receive the second digital signal output by the pipelined ADC circuit, wherein the first digital signal includes a noise transfer function, and wherein the digital filter has a digital filter function matching the noise transfer function to remove harmonic distortion from the first digital signal.

11. The ADC of claim 9 , wherein:
the first digital signal includes an error component;
the first summation circuit is configured to extract the error component and the output of the first summation circuit is a negative of the error component;
the second digital signal corresponds to the negative of the error component.

12. The ADC of claim 11 , further comprising:
a first amplifier coupled between the first summation circuit and the pipelined ADC circuit, the first amplifier configured to apply a first gain factor to the negative of the error component; and
a second amplifier coupled between the pipelined ADC circuit and the second summation circuit, the second amplifier configured to apply an inverse of the first gain factor to the second digital signal.

13. The ADC of claim 9 , further comprising a delay circuit coupled between the VCO-based Delta-Sigma ADC circuit and the second summation circuit.

14. An analog-to-digital converter (“ADC”), comprising:
an input terminal configured to receive an analog input signal;
a first ADC circuit coupled to the input terminal and including a voltage controlled oscillator (VCO), the first ADC circuit configured to output a first digital signal in a frequency domain based on the analog input signal, the first digital signal including a noise transfer function;
a first digital-to-analog converter (DAC) configured to convert the first digital signal to an analog output signal;
a first summation circuit configured to receive the analog output signal and the analog input signal;
a second ADC circuit configured to convert an output of the first summation circuit to a second digital signal; and
a digital filter coupled to receive the second digital signal output by the second ADC circuit, wherein the digital filter has a digital filter function matching the noise transfer function to remove harmonic distortion from the first digital signal.

15. The ADC of claim 14 , wherein the first ADC circuit includes a Delta-Sigma ADC.

16. The ADC of claim 14 , wherein the second ADC circuit includes a pipelined ADC.

17. The ADC of claim 14 , wherein the first digital signal includes an error component, the first summation circuit being configured to further receive a filtered version of the analog input signal and extract the error component and output a negative of the error component, and wherein the ADC further comprises:
a second summation circuit configured to an output of the digital filter and the first digital signal, and output a digital output signal corresponding to the analog input signal at an output terminal.

18. The ADC of claim 17 , further comprising:
a first amplifier coupled between the first summation circuit and the second ADC circuit, the first amplifier configured to apply a first gain factor to the negative of the error component; and
a second amplifier coupled between the digital filter and the second summation circuit, the second amplifier configured to apply an inverse of the first gain factor to the second digital signal.

19. The ADC of claim 18 , wherein the first amplifier includes a transimpedance amplifier.

20. The ADC of claim 17 , wherein the error component includes a quantization error and a harmonic distortion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kinyua Martin
• Soenen Eric

Classifications

• H03M3/412

  characterised by the number of quantisers and their type and resolution · CPC title

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/12 Primary

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/368 Primary

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title