Semiconductor device and operating method thereof

Patent metadata

Field	Value
Publication number	US-10404270-B2
Application number	US-201816013985-A
Country	US
Kind code	B2
Filing date	Jun 21, 2018
Priority date	Dec 6, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC.

First claim

What is claimed is:

1. A semiconductor device comprising:
a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal;
a first analog to digital converter (ADC) that receives the residue signal and generates a first digital representation;
a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal; and
a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal,
wherein the first ADC is a multi-bit Successive Approximation Register ADC using a first step voltage.

2. The semiconductor device of claim 1 , wherein the second ADC is a multi-bit SAR ADC using a second step voltage less than or equal to the first step voltage.

3. The semiconductor device of claim 1 , further comprising:
a first node that performs a subtraction operation between the analog input signal and the feedback signal to generate the differential analog signal.

4. The semiconductor device of claim 3 , wherein the loop filter further comprises:
a gain block that receives the differential analog signal and performs a scaling operation on the differential analog signal to generate a scaled result;
a first integrator that receives the scaled result and performs a first integral operation on the scaled result to generate a first integrated result;
a first filter and a second filter that commonly receive the first integrated result, and respectively perform a first filter operation and a second filter operation;
first sub-node that adds an output of the first filter to an output of the second filter to generate a summation result; and
a second integrator which receives an output of the second node, performs a second integral operation to generate a second integrated result, and provides the second integrated result to the first ADC.

5. The semiconductor device of claim 4 , wherein the loop filter further comprises:
a second sub-node that performs a subtraction operation between the second integrated result and the first digital representation provided by the first ADC; and
a third filter that receives an output signal of the second sub-node and performs a third filter operation,
wherein the first sub-node performs a subtraction operation between an output of the third filter and the summation result.

6. The semiconductor device of claim 1 , further comprising:
a Signal Transfer Function (STF) block that receives the second digital representation from the second ADC and performs a preset digital signal processing.

7. The semiconductor device of claim 6 , further comprising:
a third node that adds an output of the STF block to the first digital representation from the first ADC.

8. The semiconductor device of claim 7 , further comprising:
a decimator that receives an output of the third node to generates a final digital output having N-bits, where ‘N’ is a natural number.

9. The semiconductor device of claim 1 , wherein the second ADC is a coarse ADC, and the first ADC is a fine ADC.

10. A semiconductor device comprising:
a first node that performs a subtract operation between an analog input signal and a feedback signal to generate a differential analog signal;
a second node that performs an addition operation on a first digital representation and a second digital representation;
a digital to analog converter (DAC) that generates the feedback signal from an output of the second node;
a gain block that performs an amplification operation on the differential analog signal;
a first integrator that performs a first integral operation on the amplified differential analog signal to generate a first integrated result;
a first filter that performs a first filter operation on the first integrated result, and a second filter that performs a second filter operation on the first integrated result;
a first sub-node node that performs an addition operation on an output of the first filter and an output of the second filter;
a second integrator that performs a second integral operation of an output of the first sub-node to generate a second integrated result; and
a fine analog to digital converter (ADC) that generates the first digital representation from the second integral result.

11. The semiconductor device of claim 10 , further comprising:
a coarse ADC that that generates the second digital representation from the analog input signal;
a Signal Transfer Function (STF) block that receives the second digital representation and performs a preset digital signal processing;
a third node performs an addition operation on an output of the STF block and the first digital representation; and
a decimator that receives an output of the third node to generates a final digital output having N-bits, where ‘N’ is a natural number.

12. A method of operating a semiconductor device, the method comprising:
generating a residue signal indicating an error between an analog input signal and a feedback signal using a loop filter that receives a differential analog signal;
generating a first digital representation from the residue signal using a first analog to digital converter (ADC);
generating a second digital representation from the analog input signal using a second ADC; and
generating the feedback signal using a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation,
wherein the first ADC is a multi-bit Successive Approximation Register ADC using a first step voltage.

13. The method of claim 12 , wherein the second ADC is a multi-bit SAR ADC using a second step voltage less than or equal to the first step voltage.

14. The method of claim 12 , further comprising:
performing a subtraction operation at a first node between the analog input signal and the feedback signal to generate the differential analog signal.

15. The method of claim 14 , further comprising:
performing a scaling operation on the differential analog signal using a gain block to generate a scaled result;
performing a first integral operation on the scaled result to generate a first integrated result using a first integrator;
performing a first filtering operation on the first integrated result using a first filter;
performing a second filtering operation on the first integrated result using a second filter;
adding an output of the first filter to an output of the second filter at a first sub-node to generate a summation result.

16. The method of claim 15 , further comprising:
performing a subtraction operation between the second integrated result and the first digital representation at a second sub-node;
performing a third filter operation on an output of the second sub-node using a third filter; and
performing a subtraction operation between a result of the third filter operation and the summation result.

17. The method of claim 12 , further comprising:
performing a preset digital signal processing on the second digital representation using a Signal Transfer Function (STF) block.

18. The method of claim 17 , further comprising:
adding an output of the STF block to the first digital representation at a third node.

19. The method of claim 18 , further comprising:
generating a final digital output having N-bits, where ‘N’ is a natural number, from an output of the third node using a decimator.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Na Seung In
• Park Da Som

Classifications

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/145

  the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence) · CPC title