Structures to facilitate heat transfer within package layers to thermal heat sink and motherboard

Patent metadata

Field	Value
Publication number	US-11437294-B2
Application number	US-201816059513-A
Country	US
Kind code	B2
Filing date	Aug 9, 2018
Priority date	Aug 9, 2018
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

First claim

What is claimed is:

1. An electronics package, comprising:
a package substrate, wherein the package substrate comprises:
a plurality of backside layers;
a plurality of front-side layers; and
a core layer between the plurality of backside layers and the plurality of front-side layers;

an inductor embedded in the plurality of backside layers; and
a plurality of bumps over the front-side layers and thermally coupled to the inductor, wherein the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

2. The electronics package of claim 1 , wherein the plurality of front-side layers each comprise a conductive pad and a dielectric layer, and wherein the pads are thermally coupled to each other by the plurality of vias that pass through the dielectric layers.

3. The electronics package of claim 2 , wherein the plurality of bumps comprise a first group of bumps that are electrically in parallel and adjacent to each other, and wherein the first group of bumps are positioned on an isolated first pad.

4. The electronics package of claim 3 , wherein the plurality of bumps further comprise a second group of bumps that are electrically in parallel and adjacent to each other, and wherein the second group of bumps are positioned on an isolated second pad.

5. The electronics package of claim 4 , wherein the first group of bumps comprises a different number of bumps than the second group of bumps.

6. The electronics package of claim 3 , wherein the first group of bumps form a ring around a power domain of the electronics package.

7. The electronics package of claim 1 , wherein the plurality of vias have a width dimension that is not substantially equal to a length dimension.

8. The electronics package of claim 1 , wherein the plurality of vias are merged to form a block between each of the front-side layers.

9. The electronics package of claim 1 , wherein a second plurality of vias are merged to form a block between one or more of the backside layers.

10. The electronics package of claim 1 , wherein the plurality of vias are merged to form a block between each of the front-side layers, and wherein a second plurality of vias are merged to form a block between one or more of the backside layers.

11. The electronics package of claim 1 , wherein the bumps are coupled to a die.

12. The electronics package of claim 11 , wherein the die is thermally coupled to a heat sink.

13. The electronics package of claim 12 , wherein the inductor is thermally coupled to the heat sink by the plurality of vias and the plurality of bumps.

14. The electronics package of claim 1 , further comprising a power domain that does not comprise an inductor, and a second plurality of bumps over the front-side layers and thermally coupled to the power domain by vias.

15. An electronics package, comprising:
a package substrate, wherein the package substrate comprises:
a plurality of backside layers;
a plurality of front-side layers; and
a core layer between the plurality of backside layers and the plurality of front-side layers;

an inductor embedded in the plurality of backside layers; and
a thermal path below the inductor, wherein the thermal path is coupled to a backside layer of the electronics package with solder balls.

16. The electronics package of claim 15 , wherein the thermal path comprises a magnetic block.

17. The electronics package of claim 16 , wherein the magnetic block separates a ground plane from the inductor.

18. The electronics package of claim 15 , wherein the thermal path comprises a non-magnetic block.

19. The electronics package of claim 15 , wherein the electronics package is coupled to a board, and wherein solder balls between a backside layer and the board have a first height, and wherein solder balls between the thermal path and the board have a second height, wherein the second height is less than the first height.

20. The electronics package of claim 15 , wherein the thermal pathway is coupled to a board.

21. The electronics package of claim 20 , wherein the inductor is thermally coupled to the board.

22. An electronics package, comprising:
a package substrate, wherein the package substrate comprises:
a plurality of backside layers;
a plurality of front-side layers; and
a core layer between the plurality of backside layers and the plurality of front-side layers;

an inductor embedded in the plurality of backside layers; and
a thermal path below the inductor, wherein the thermal path comprises a magnetic block.

23. An electronics package, comprising:
a package substrate, wherein the package substrate comprises:
a plurality of backside layers;
a plurality of front-side layers; and
a core layer between the plurality of backside layers and the plurality of front-side layers;

an inductor embedded in the plurality of backside layers, wherein the inductor comprises a first conductive material; and
a thermal sink attached to the inductor, wherein the thermal sink is a second conductive material that is different than the first conductive material.

24. The electronics package of claim 23 , wherein edges of the thermal sink are coplanar with edges of the inductor.

25. The electronics package of claim 23 , wherein the second conductive material has a thermal capacity that is greater than a thermal capacity of the first conductive material.

Assignees

• Intel Corp

Inventors

• Shekhar Sameer
• Jain Amit Kumar
• Radhakrishnan Kaladhar
• Douglas Jonathan P
• Kuan Chin Lee

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title