Contact over active gate structure

Patent metadata

Field	Value
Publication number	US-11437284-B2
Application number	US-201916550784-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Aug 31, 2018
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

First claim

What is claimed is:

1. A method of forming a contact, the method comprising:
forming at least one gate stack over an active region on a substrate, the at least one gate stack having a first side and a second side and comprising a gate and a gate cap comprising a first material, the substrate having a spacer material adjacent the first side and the second side of the at least one gate stack, a source material with a source cap comprising a second material on an opposite side of the spacer material adjacent the first side of the at least one gate stack, a drain material with a drain cap comprising the second material on an opposite side of the spacer material adjacent the second side of the at least one gate stack;
forming an interlayer dielectric (ILD) comprising the second material on the gate cap, spacer material, source cap, and drain cap, and a first mask layer on the interlayer dielectric (ILD), the interlayer dielectric (ILD) and the first mask layer having at least one opening exposing a surface of the gate cap, a surface of the spacer material, a surface of the source material, and a surface of the drain material;
selectively etching one of the source cap or the drain cap through the at least one opening to expose one of a surface of the source material or a surface of the drain material;
selectively depositing a fill material on one of the exposed surface of the source material or the exposed surface of the drain material, the fill material having a top surface substantially coplanar with a top surface of the spacer material and with a top surface of the drain cap or a top surface of the source cap;
removing the gate cap to expose a surface of the gate;
forming a gate contact on one of the surface of the gate, the surface of the source material, or the surface of the drain material; and
forming a source/drain contact on one or more of the surface of the gate material, the surface of the drain material, the surface of the spacer material, or the surface of the gate cap.

2. The method of claim 1 , wherein the fill material is selected from one or more of hafnium oxide, zirconium oxide, aluminum oxide, silicon oxide, silicon nitride, or the like.

3. The method of claim 1 , wherein the gate comprises a metal selected from one or more of cobalt, tungsten, titanium, molybdenum, nickel, ruthenium, silver, iridium, or platinum.

4. The method of claim 1 , wherein the first material comprises one or more of silicon carbide, tungsten oxide, tungsten carbide, silicon nitride, aluminum oxide, or zirconium oxide.

5. The method of claim 1 , wherein the spacer material comprises a low-κ dielectric.

6. The method of claim 5 , wherein the low-κ dielectric comprises one or more of silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

7. The method of claim 1 , wherein the second material comprises one or more of silicon nitride, silicon oxynitride, or silicon oxide.

8. The method of claim 1 , wherein the first mask layer comprises a third material selected from one or more of a spin-on carbon, hardmask, or a photoresist.

9. The method of claim 1 , wherein the gate contact and the source/drain contact independently comprises one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), or platinum (Pt).

10. A method of forming a contact, the method comprising:
forming at least one gate stack over an active region on a substrate, the at least one gate stack having a first side and a second side and comprising a gate and a gate cap comprising a first material, the substrate having a spacer material adjacent the first side and the second side of the at least one gate stack, a source material with a source cap comprising a second material on an opposite side of the spacer material adjacent the first side of the at least one gate stack, a drain material with a drain cap comprising the second material on an opposite side of the spacer material adjacent the second side of the at least one gate stack;
forming an interlayer dielectric (ILD) comprising the second material on the gate cap, spacer material, source cap, and drain cap;
forming a first mask layer on the interlayer dielectric (ILD), the interlayer dielectric (ILD) and the first mask layer having at least one opening;
selectively etching one of the source cap or the drain cap through the at least one opening to expose one of a surface of the source material or a surface of the drain material;
selectively depositing a fill material on one of the exposed surface of the source material or the exposed surface of the drain material, the fill material having a top surface substantially coplanar with a top surface of the spacer material and with a top surface of the drain cap or a top surface of the source cap;
removing the gate cap to expose a surface of the gate; and
forming a gate contact on the surface of the gate.

11. The method of claim 10 , wherein the fill material is selected from one or more of hafnium oxide, zirconium oxide, aluminum oxide, silicon oxide, silicon nitride, or the like.

12. The method of claim 10 , wherein the gate comprises a metal selected from one or more of cobalt, tungsten, titanium, molybdenum, nickel, ruthenium, silver, iridium, or platinum.

13. The method of claim 10 , wherein the first material comprises one or more of silicon carbide, tungsten oxide, tungsten carbide, silicon nitride, aluminum oxide, or zirconium oxide.

14. The method of claim 10 , wherein the spacer material comprises a low-κ dielectric.

15. The method of claim 10 , wherein the second material comprises one or more of silicon nitride, silicon oxynitride, or silicon oxide.

16. The method of claim 10 , wherein the first mask layer comprises a third material selected from one or more of a spin-on carbon, hardmask, or a photoresist.

17. The method of claim 10 , wherein the gate contact comprises one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Jr), or platinum (Pt).

Assignees

• Applied Materials Inc

Inventors

• Wang Wenhui
• Dai Huixiong
• Ngai Christopher S

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10D64/01

  Manufacture or treatment · CPC title