Showerhead device for semiconductor processing system

Patent metadata

Field	Value
Publication number	US-11437249-B2
Application number	US-202016930800-A
Country	US
Kind code	B2
Filing date	Jul 16, 2020
Priority date	Jul 18, 2019
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

To create constant partial pressures of the by-products and residence time of the gas molecules across the wafer, a dual showerhead reactor can be used. A dual showerhead structure can achieve spatially uniform partial pressures, residence times and temperatures for the etchant and for the by-products, thus leading to uniform etch rates across the wafer. The system can include differential pumping to the reactor.

First claim

What is claimed is:

1. A semiconductor processing apparatus, comprising:
a reaction chamber and a reaction chamber exhaust port, the reaction chamber exhaust port configured to remove vapors from the reaction chamber;
a showerhead device connected to the reaction chamber and configured to deliver reactant vapors to the reaction chamber, the showerhead device comprising:
a gas inlet configured to supply the reactant vapors into the showerhead device;
a first showerhead plate in fluid communication with the gas inlet, the first showerhead plate comprising a plurality of openings;
a plenum disposed between the gas inlet and the first showerhead plate, the plenum configured to convey vapors from the gas inlet to the plurality of openings; and
a second showerhead plate comprising:
a plurality of inlet ports in fluid communication with the plurality of openings, the plurality of inlet ports configured to deliver the reactant vapors to the reaction chamber; and
a plurality of outlet apertures configured to remove vapors from the reaction chamber; and

one or more pumps connected to the reaction chamber exhaust port and the plurality of outlet apertures, the one or more pumps configured to remove vapors from the reaction chamber through the reaction chamber exhaust port and the plurality of outlet apertures;
wherein the first and second showerhead plates cooperate to define a channel in fluid communication with the plurality of outlet apertures and the one or more pumps;
wherein the showerhead device comprises an upper portion and a lower portion separated by the plenum, the upper portion comprising a second plurality of openings and the lower portion comprising the first and second showerhead plates.

2. The semiconductor processing apparatus of claim 1 , wherein the one or more pumps comprises a plurality of pumps.

3. The semiconductor processing apparatus of claim 1 , further comprising a susceptor within the reaction chamber facing the showerhead device.

4. The semiconductor processing apparatus of claim 3 , further comprising a motor drive connected to the susceptor, the motor drive configured to adjust the distance between the susceptor and the showerhead device.

5. The semiconductor processing apparatus of claim 4 , further comprising a control system in electrical communication with the motor drive, the control system configured to adjust the distance between the susceptor and the showerhead device during etching.

6. The semiconductor processing apparatus of claim 1 , wherein the plurality of inlet ports bypasses the channel.

7. The semiconductor processing apparatus of claim 1 , wherein the channel forms a zig-zag pattern.

8. The semiconductor processing apparatus of claim 1 , wherein the plurality of outlet apertures are located along concentric rings on the second plate.

9. The semiconductor processing apparatus of claim 1 , wherein the gas inlet comprises a plurality of branched inlet lines that deliver the reactant vapors to the first showerhead plate.

10. The semiconductor processing apparatus of claim 1 , further comprising a control system configured to deliver an etch reactant from an etch reactant source to the reaction chamber.

11. The semiconductor processing apparatus of claim 10 , further comprising the etch reactant source in fluid communication with the first showerhead plate.

12. The semiconductor processing apparatus of claim 11 , wherein the control system is configured to deliver the etch reactant to a substrate conformally such that etch conformality is greater than 50%.

13. The semiconductor processing apparatus of claim 11 , wherein the control system is configured to deliver the etch reactant to a substrate selectively such that the etch selectivity is greater than 10%.

14. A semiconductor processing apparatus, comprising:
a reaction chamber;
a reaction chamber exhaust port configured to remove vapors from the reaction chamber; and
a showerhead device comprising:
a plurality of distributed inlet apertures in fluid communication with a reaction vapor source and the reaction chamber;
a gas inlet configured to supply reactant vapors into the showerhead device;
a plenum disposed between the gas inlet and the inlet apertures, the plenum configured to convey vapors from the gas inlet to the inlet apertures; and
a plurality of distributed exhaust apertures in fluid communication with a pump and the reaction chamber, the plurality of distributed exhaust apertures configured to remove vapors from the reaction chamber;
wherein the showerhead device comprises an upper portion and a lower portion separated by the plenum;
wherein the showerhead device comprises a first showerhead plate disposed over a second showerhead plate;
wherein the lower portion of the showerhead device comprises the first and second showerhead plates, and the upper portion comprises a second plurality of exhaust apertures;
wherein the first and second showerhead plates cooperate to define a channel in fluid communication with the plurality of exhaust apertures and the pump.

15. The semiconductor processing apparatus of claim 14 , wherein the first showerhead plate includes a plurality of inlet openings, and wherein the second showerhead plate includes a plurality of inlet ports and a plurality of exhaust ports.

16. The semiconductor processing apparatus of claim 14 , further comprising a gas inlet including a plurality of branched gas inlet lines to deliver vapors to the showerhead device.

17. A semiconductor processing apparatus, comprising:
a reaction chamber; and
a showerhead device comprising:
a gas inlet configured to supply reactant vapors into the showerhead device;
an internal plenum communicating with a pump;
a plurality of exhaust apertures in fluid communication with the internal plenum and the reaction chamber, the plurality of exhaust apertures configured to remove vapors from the reaction chamber;
a plurality of inlet apertures in fluid communication with a reaction vapor source and the reaction chamber, the inlet apertures extending through the showerhead device and bypassing the internal plenum, the inlet apertures in fluid communication with an upper plenum, and the upper plenum disposed between the gas inlet and the showerhead device;
wherein the internal plenum comprises a zig-zag pattern;
wherein the showerhead device comprises two showerhead plates, and the zig-zag pattern is defined by a groove in one of the plates that is covered by the other of the plates.

18. The semiconductor processing apparatus of claim 17 , further comprising a reaction chamber exhaust port.

19. The semiconductor processing apparatus of claim 17 , further comprising one or more pumps in fluid communication with the plurality of exhaust apertures.

20. The semiconductor processing apparatus of claim 1 , further comprising an inlet manifold, the inlet manifold disposed between the gas inlet and the plenum.

Assignees

• Asm Ip Holding Bv

Inventors

• Blomberg Tom E
• Sharma Varun

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P72/0418 Primary

  for etching · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title

• H10P72/0402

  Apparatus for fluid treatment (H10P72/0441, H10P72/0448 take precedence) · CPC title

• H10P72/0424 Primary

  using mainly spraying means, e.g. nozzles · CPC title